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ADC0844 Просмотр технического описания (PDF) - National ->Texas Instruments

Номер в каталогеADC0844 National-Semiconductor
National ->Texas Instruments National-Semiconductor
Компоненты Описание8-Bit μP Compatible A/D Converters with Multiplexer Options
ADC0844 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Parameter
Conditions
VOUT(0), Logical “0” Output Voltage (Max)
VCC=4.75V,
IOUT=1.6 mA
IOUT, TRI-STATE Output Current (Max)
VOUT=0V
VOUT=5V
ISOURCE, Output Source Current (Min) VOUT=0V
ISINK, Output Sink Current (Min)
VOUT=VCC
ICC, Supply Current (Max)
CS =1, VREF Open
ADC0844BCJ (Note 12)
ADC0844CCJ (Note 12)
ADC0844CCN
ADC0848BCN, ADC0848CCN
ADC0848BCV, ADC0848CCV Limit
Tested Design
Tested
Typ
(Note 5)
Limit
(Note 6)
Limit
(Note 7)
Typ
(Note 5)
Limit
(Note 6)
Design Units
Limit
(Note 7)
V
0.4
0.34
0.4
V
−0.01
−3
0.01
3
−14
−6.5
16
8.0
1
2.5
−0.01 −0.3
0.01
0.3
−14
−7.5
16
9.0
1
2.3
−3
μA
3
μA
−6.5 mA
8.0
mA
2.5
mA
AC Electrical Characteristics
The following specifications apply for VCC = 5VDC, tr = tf = 10 ns unless otherwise specified. Boldface limits apply from TMIN to
TMAX; all other limits TA = Tj = 25°C.
Parameter
Conditions
Typ
(Note 5)
Tested
Limit
(Note 6)
Design
Limit
(Note 7)
Units
tC, Maximum Conversion Time (See Graph)
30
40
60
μs
tW(WR), Minimum WR Pulse Width
(Note 11)
50
150
ns
tACC, Maximum Access Time (Delay from Falling Edge of RD to
Output Data Valid)
CL = 100 pF (Note 11)
145
225
ns
t1H, t0H, TRI-STATE Control (Maximum Delay from Rising Edge CL = 10 pF, RL = 10k
125
of RD to Hi-Z State)
(Note 11)
200
ns
tWI, tRI, Maximum Delay from Falling Edge of WR or RD to Reset (Note 11)
200
400
ns
of INTR
tDS, Minimum Data Set-Up Time
tDH, Minimum Data Hold Time
CIN, Capacitance of Logic Inputs
COUT, Capacitance of Logic Outputs
(Note 11)
(Note 11)
50
100
ns
0
50
ns
5
pF
5
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the ground pins.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < Vor VIN > V+) the absolute value of the current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5: Typical figures are at 25°C and represent most likely parametric norm.
Note 6: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 7: Design limits are guaranteed by not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 8: Total unadjusted error includes offset, full-scale, linearity, and multiplexer error.
Note 9: For VIN (−) VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward-conduct for analog
input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at low VCC levels (4.5V), as high level analog
inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV
forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct.
To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial
tolerance and loading.
Note 10: Off channel leakage current is measured after the channel selection.
Note 11: The temperature coefficient is 0.3%/°C.
Note 12: This product/package combination is obsolete. Shown for reference only.
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