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ADC0833 Просмотр технического описания (PDF) - National ->Texas Instruments

Номер в каталогеADC0833 National-Semiconductor
National ->Texas Instruments National-Semiconductor
Компоненты Описание8-Bit Serial I/O A/D Converter with 4-Channel Multiplexer
ADC0833 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
Functional Description (Continued)
4 When the start bit has been shifted into the start location
of the MUX register the input channel has been assigned
and a conversion is about to begin An interval of clock
period (where nothing happens) is automatically inserted to
allow the selected MUX channel to settle The SAR status
line goes high at this time to signal that a conversion is now
in progress and the DI line is disabled (it no longer accepts
data)
5 The data out (DO) line now comes out of TRI-STATE and
provides a leading zero for this one clock period of MUX
settling time
6 When the conversion begins the output of the SAR com-
parator which indicates whether the analog input is greater
than (high) or less than (low) each successive voltage from
the internal resistor ladder appears at the DO line on each
falling edge of the clock This data is the result of the con-
version being shifted out (with the MSB coming first) and
can be read by the processor immediately
7 After 8 clock periods the conversion is completed The
SAR status line returns low to indicate this clock cycle
later
8 If the programmer prefers the data can be read in an LSB
first format All 8 bits of the result are stored in an output
shift register The conversion result LSB first is automati-
cally shifted out the DO line after the MSB first data stream
The DO line then goes low and stays low until CS is re-
turned high
9 All internal registers are cleared when the CS line is high
If another conversion is desired CS must make a high to
low transition followed by address information
The DI and DO lines can be tied together and controlled
through a bidirectional processor I O bit with one wire This
is possible because the DI input is only ‘‘looked-at’’ during
the MUX addressing interval while the DO line is still in a
high impedance state
3 0 REFERENCE CONSIDERATIONS
The ADC0833 is intended primarily for use in circuits requir-
ing absolute accuracy In this type of system the analog
inputs vary between very specific voltage limits and the ref-
erence voltage for the A D converter must remain stable
with time and temperature For ratiometric applications an
ADC0834 is a pin-for-pin compatible alternative since it has
a VREF input (note the ADC0834 needs one less bit of mux
addressing information)
The voltage applied to the VREF 2 pin defines the voltage
span of the analog input the difference between VIN(a)
and VIN(b) over which the 256 possible output codes ap-
ply A full-scale conversion (an all 1s output code) will result
when the voltage difference between a selected ‘‘a’’ input
and ‘‘b’’ input is approximately twice the voltage at the
VREF 2 pin This internal gain of 2 from the applied refer-
ence to the full-scale input voltage allows biasing a low volt-
age reference diode from the 5VDC converter supply To
accommodate a 5V input span only a 2 5V reference is
required The LM385 and LM336 reference diodes are good
low current devices to use with these converters The out-
put code changes in accordance with the following equa-
tion
 J Output Codee256 VIN(a) b VIN(b)
2(VREF 2)
where the output code is the decimal equivalent of the 8-bit
binary output (ranging from 0 to 255) and the term VREF 2 is
the voltage from pin 9 to ground
The VREF 2 pin is the center point of a two resistor divider
(each resistor is 3 5 kX) connected from VCC to ground
Total ladder input resistance is the sum of these two equal
resistors As shown in Figure 2 a reference diode with a
voltage less than VCC 2 can be connected without requiring
an external biasing resistor if its current requirements meet
the indicated level
The minimum value of VREF 2 can be quite small (see Typi-
cal Performance Characteristics) to allow direct conversions
of transducer outputs providing less than a 5V output span
Particular care must be taken with regard to noise pickup
circuit layout and system error voltage sources when oper-
ating with a reduced span due to the increased sensitivity of
the converter (1 LSB equals VREF 256)
VFULL-SCALEj2 4V
VFULL-SCALEj5 0V
Note
No
external
biasing
resistor
needed
if
VZ
k
VCC
2
and
IZ
min
k
VCC 2
1 75
b VZ
kX
FIGURE 2 Reference Biasing Examples
11
TL H 5607 – 7
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