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ADC0816 Просмотр технического описания (PDF) - National ->Texas Instruments

Номер в каталогеADC0816 National-Semiconductor
National ->Texas Instruments National-Semiconductor
Компоненты Описание8-Bit μP Compatible A/D Converters with 16-Channel Multiplexer
ADC0816 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Symbol
Parameter
CONTROL INPUTS
VIN(1)
VIN(0)
IIN(1)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
(The Control Inputs)
IIN(0)
Logical “0” Input Current
(The Control Inputs)
ICC
Supply Current
DATA OUTPUTS AND EOC (INTERRUPT)
VOUT(1)
Logical “1” Output Voltage
VOUT(0)
VOUT(0)
IOUT
Logical “0” Output Voltage
Logical “0” Output Voltage EOC
TRI-STATE Output Current
Conditions
VIN=15V
VIN=0
fCLK=640 kHz
IO=−360 μA, TA=85°C
IO=−300 μA, TA=125°C
IO=1.6 mA
IO=1.2 mA
VO=VCC
VO=0
Min
Typ
VCC − 1.5
−1.0
0.3
Max
1.5
1.0
3.0
Units
V
V
μA
μA
mA
VCC − 0.4
−3.0
V
0.45
V
0.45
V
3.0
μA
μA
Electrical Characteristics
Timing Specifications: VCC=VREF(+)=5V, VREF(−)=GND, tr=tf=20 ns and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min Typ
tWS
Minimum Start Pulse Width
(Figure 5) (Note 7)
100
tWALE
Minimum ALE Pulse Width
(Figure 5)
100
ts
Minimum Address Set-Up Time (Figure 5)
25
TH
Minimum Address Hold Time
(Figure 5)
25
tD
Analog MUX Delay Time
from ALE
RS=OΩ (Figure 5)
1
tH1, tH0
t1H, t0H
tC
fc
OE Control to Q Logic State
OE Control to Hi-Z
Conversion Time
Clock Frequency
CL=50 pF, RL=10k (Figure 8)
CL=10 pF, RL=10k (Figure 8)
fc=640 kHz, (Figure 5) (Note 8)
125
125
90 100
10 640
Max
200
200
50
50
2.5
250
250
116
1280
tEOC
EOC Delay Time
(Figure 5)
0
8 + 2μs
CIN
COUT
Input Capacitance
TRI-STATE Output
Capacitance
At Control Inputs
At TRI-STATE Outputs (Note 8)
10
15
10
15
Units
ns
ns
ns
ns
μs
ns
ns
μs
kHz
Clock
Periods
pF
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: A Zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop
greater than the VCC supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage
by more than 100 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage
of 4.900 VDC over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, and linearity errors. See Figure 3. None of these A/Ds requires a zero or full-scale adjust. However, if
an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages
can be adjusted to achieve this. See Figure 13.
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has
little temperature dependence (Figure 6). See paragraph 4.0.
Note 7: If start pulse
at fc 640 kHz take
is asynchronous
start high within
with
100
converter clock or if fc
ns of clock going low.
>
640
kHz,
the
minimum
start
pulse
width
is
8
clock
periods
plus
2
μs.
For
synchronous
operation
Note 8: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 9: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
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