|Номер в каталоге||ADC08131|
National ->Texas Instruments
|Компоненты Описание||8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, Voltage Reference, and Track/Hold Function|
|ADC08131 Datasheet PDF : 22 Pages |
Electrical Characteristics (Continued)
The following specifications apply for VCC = +5 VDC, VREF = +2.5 VDC and tr = tf = 20 ns unless otherwise specified. Boldface
limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Conversion Time (Not Including
MUX Addressing Time)
fCLK = 1 MHz
CLK High while CS is High
CS Falling Edge or Data Input
Valid to CLK Rising Edge
Data Input Valid after CLK Rising
CLK Falling Edge to Output Data
Valid (Note 15)
CL = 100 pF:
Data MSB First
Data LSB First
TRI-STATE Delay from Rising Edge CL = 10 pF, RL = 10 kΩ
of CS to Data Output and SARS
(see TRI-STATE Test Circuits)
CL = 100 pF, RL = 2 kΩ
Capacitance of Logic Inputs
Capacitance of Logic Outputs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed
specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to AGND = DGND = 0 VDC, unless otherwise specified.
Note 4: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < (AGND or DGND) or VIN > AVCC) the current at that pin should be limited to
5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For these
devices TJMAX = 125˚C. The typical thermal resistances (θJA) of these parts when board mounted for the ADC 08131 and the ADC08134 is 140˚C/W and 91˚C/W
for the ADC08138.
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor.
Note 7: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or Linear Data Book section “Surface Mount” for other methods of soldering
surface mount devices.
Note 8: Typicals are at TJ = 25˚C and represent the most likely parametric norm.
Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error includes zero, full-scale, linearity, and multiplexer error. Total unadjusted error with VREF = +5V only applies to the ADC08134 and
ADC08138. See (Note 16).
Note 11: Cannot be tested for the ADC08131.
Note 12: For VIN(−) ≥ VIN(+) the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct
for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. During testing at low VCC levels (e.g., 4.5V), high level analog
inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full-scale. The specification
allows 50 mV forward bias of either diode; this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will
be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 VDC to 5 VDC input voltage
range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading.
Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, with the selected channel tied high (5 VDC) and the remaining seven off channels tied low (0 VDC), total current flow through the off
channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two
cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits
the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 µs.
Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow
for comparator response time.
Note 16: For the ADC08131 VREFIN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger because it includes the
reference current (700 µA typical, 2 mA maximum).
Note 17: Load regulation test conditions and specifications for the ADC08131 differ from those of the ADC08134 and ADC08138 because the ADC08131 has the
on-board reference as a permanent load.
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