MAX145ACPA View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX145ACPA Datasheet PDF : 16 Pages
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+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
fication, and the first four data bits starting with the
MSB. The second 8-bit data stream contains the
remaining bits, D7 through D0.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX144/MAX145 support a maxi-
mum fSCLK of 2.17MHz. The QSPI circuit in Figure 9a
can be programmed to perform a conversion on each
of the two channels for the MAX144. Figure 9b shows
the QSPI interface timing.
CS
SCK
MISO
QSPI
VDD
SS
Figure 9a. QSPI Connections
CS/SHDN
SCLK
DOUT
MAX144
MAX145
PIC16 with SSP Module and PIC17 Interface
The MAX144/MAX145 are compatible with a PIC16/
PIC17 controller (µC), using the synchronous serial-port
(SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
port control register (SSPCON) and synchronous serial-
port status register (SSPSTAT) to the bit patterns shown
in Tables 2 and 3.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be synchronously transmitted and received simulta-
neously. Two consecutive 8-bit readings (Figure 10b)
are necessary to obtain the entire 12-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µC on SCLK’s rising edge.
The first 8-bit data stream contains three leading ones,
the channel identification, and the first four data bits
starting with the MSB. The second 8-bit data stream
contains the remaining bits, D7 through D0.
SCLK
CS/SHDN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DOUT
CHID D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SAMPLING INSTANT MSB
LSB
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
HIGH-Z
Table 2. Detailed SSPCON Register Contents
CONTROL BIT
WCOL
SSPOV
BIT7
BIT6
MAX144/MAX145
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
X
Write Collision Detection Bit
X
Receive Overflow Detect Bit
SSPEN BIT5
Synchronous Serial-Port Enable Bit.
1
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins.
CKP
SSPM3
SSPM2
SSPM1
SSPM0
BIT4
BIT3
BIT2
BIT1
BIT0
0
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
0
0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects
0
fCLK = fOSC / 16.
1
X = Don’t care
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