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AD9952 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD9952 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer ADI
Analog Devices ADI
AD9952 Datasheet PDF : 28 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD9952
Parameter
Wake-Up Time4
Minimum Reset Pulse Width High
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE, SYNC_CLK Hold Time
Latency
I/O UPDATE to Frequency Change Prop Delay
I/O UPDATE to Phase Offset Change Prop Delay
I/O UPDATE to Amplitude Change Prop Delay
CMOS LOGIC INPUTS
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V
Logic 1 Voltage
Logic 0 Voltage
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V
Logic 1 Voltage
Logic 0 Voltage
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)
Single-Tone Mode
Rapid Power-Down Mode
Full-Sleep Mode
SYNCHRONIZATION FUNCTION6
Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V)
Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V)
SYNC_CLK Alignment Resolution7
Temp Min
FULL
FULL 5
FULL 4
FULL 6
FULL 0
25°C 24
25°C 24
25°C 16
25°C 1.25
25°C
25°C 2.2
25°C
25°C
25°C
25°C
25°C 1.35
25°C
25°C 2.8
25°C
25°C
25°C
25°C
25°C 62.5
25°C 100
25°C
Typ Max
1
0.6
0.8
3
12
12
2
0.4
0.4
162 171
150 160
20
27
±1
Unit
ms
SYSCLK Cycles5
ns
ns
ns
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
V
V
V
V
µA
µA
pF
V
V
V
V
mW
mW
mW
MHz
MHz
SYSCLK Cycles
1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise
performance of the device.
2 Represents the cycle-to-cycle residual jitter from the comparator alone.
3 Represents the cycle-to-cycle residual jitter from the DDS core driving the comparator.
4 Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions of the AD9952 section). The longest time required is for the
reference clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values
are used.
5 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency.
6 SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.
7 This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
Rev. 0 | Page 6 of 28
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