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AD9952 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD9952 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer ADI
Analog Devices ADI
AD9952 Datasheet PDF : 28 Pages
First Prev 21 22 23 24 25 26 27 28
AD9952
When the CFR1<3> bit is 0 and the PWRDWNCTL input pin is
high, the AD9952 is put into a fast recovery power-down mode.
In this mode, the digital logic and the DAC digital logic are
powered down. The DAC bias circuitry, comparator, PLL, oscil-
lator, and clock input circuitry is not powered down. The com-
parator can be individually powered down by setting the com-
parator power-down bit, CFR1<6> = 1.
When the CFR1<3> bit is high, and the PWRDWNCTL input
pin is high, the AD9952 is put into the full power-down mode.
In this mode, all functions are powered down. This includes the
DAC and PLL, which take a significant amount of time to
power up.
When the PWRDWNCTL input pin is high, the individual
power-down bits (CFR1<7>, <5:4>) are invalid (Don’t Care)
and unused. When the PWRDWNCTL input pin is low, the
individual power-down bits control the power-down modes of
operation.
Note that the power-down signals are all designed such that a
Logic 1 indicates the low power mode and a Logic 0 indicates
the active or power-up mode.
Table 8 indicates the logic level for each power-down bit that
drives out of the AD9952 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
Layout Considerations
For the best performance, the following layout guidelines
should be observed. Always provide the analog power supply
(AVDD) and the digital power supply (DVDD) on separate
supplies, even if just from two different voltage regulators
driven by a common supply. Likewise, the ground connections
(AGND, DGND) should be kept separate as far back to the
source as possible (i.e., separate the ground planes on a local-
ized board, even if the grounds connect to a common point in
the system). Bypass capacitors should be placed as close to the
device pin as possible. Usually, a multitiered bypassing scheme
consisting of a small high frequency capacitor (100 pF) placed
close to the supply pin and progressively larger capacitors (0.1 µF,
10 µF) placed further away from the actual supply source works
best.
Table 8. Power-Down Control Functions
Control
PWRDWNCTL = 0 CFR1<3> Don’t Care
Mode Active
Software Control
PWRDWNCTL = 1 CFR1<3> = 0
PWRDWNCTL = 1 CFR1<3> = 1
External Control,
Fast Recovery Power-Down Mode
External Control,
Full Power-Down Mode
Description
Digital Power-Down = CFR1<7>
Comparator Power-Down = CFR1<6>
DAC Power-Down = CFR1<5>
Input Clock Power-Down = CFR1<4>
Digital Power-Down = 1’b1
Comparator Power-Down = 1’b0 or CFR1<6>
DAC Power-Down = 1’b0
Input Clock Power-Down = 1’b0
Digital Power-Down = 1’b1
Comparator Power-Down = 1’b1
DAC Power-Down = 1’b1
Input Clock Power-Down = 1’b1
Rev. 0 | Page 24 of 28
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