AD9860/AD9862
Table I. Rx Data Timing Table
Table Ia. CLKSEL Set Logic Low
Table Ib. CLKSEL Set Logic High
CLKSEL
ADC
Div 2 Decimate Multiplex
No
Decimation
No Mux
Mux
See Figure 8 for
Relative Timing
Timing No. 4
Rx Data = 2 ϫ CLKOUT1
CLKOUT1 = 1⁄2 ϫ CLKIN
Not Allowed
No
Div
Timing No. 3
No Mux
Rx Data = 2 ϫ CLKOUT1
CLKOUT1 = 1⁄2 ϫ CLKIN
Decimation
Timing No. 4
Mux Rx Data(MUXED) = 2 ϫ CLKOUT1
CLKOUT1 = 1⁄2 ϫ CLKIN
Low
Timing No. 3
No Mux
Rx Data = CLKOUT1
No
Decimation
CLKOUT1 = 1⁄2 ϫ CLKIN
Timing No. 4
Mux Rx Data(MUXED) = 2 ϫ CLKOUT1
CLOUT1 = 1⁄2 ϫ CLKIN
Div
Timing No. 2
No Mux
Rx Data = 1⁄2 ϫ CLKOUT1
CLOUT1 = 1⁄2 ϫ CLKIN
Decimation
Timing No. 3
Mux Rx Data(MUXED) = CLKOUT1
CLKOUT1 = 1⁄2 ϫ CLKIN
ADC
CLKSEL Div 2
No
Div
High
Div
Decimate Multiplex
No Mux
No
Decimation
Mux
See Figure 8 for
Relative Timing
Timing No. 3
Rx Data = CLKOUT1
CLKOUT1 = CLKIN
Timing No. 4
Rx Data(MUXED) = 2 ϫ CLKOUT1
CLKOUT1 = CLKIN
No Mux
Decimation
Mux
Timing No. 2
Rx Data = 1⁄2 ϫ CLKOUT1
CLKOUT1 = CLKIN
Timing No. 3
Rx Data(MUXED) = CLKOUT1
CLKOUT1 = CLKIN
No Mux
No
Decimation
Mux
Timing No. 2
Rx Data = 1⁄2 ϫ CLKOUT1
CLKOUT1 = CLKIN
Timing No. 3
Rx Data(MUXED) = CLKOUT1
CLOUT1 = CLKIN
No Mux
Timing No. 1
Rx Data = 1⁄4 ϫ CLKOUT1
CLOUT1 = CLKIN
Decimation
Timing No. 2
Mux Rx Data(MUXED) = 1⁄2 ϫ CLKOUT1
CLKOUT1 = CLKIN
fCLKOUT1
Rx DATA TIMING No. 1
fRx = CLKOUT،4
Rx DATA TIMING No. 2
fRx = CLKOUT،2
Rx DATA TIMING No. 3
fRx = CLKOUT
Rx DATA TIMING No. 4
fRx = 2؋CLKOUT
tR؋1
tR؋2
tR؋3
tR؋1
Figure 9. Rx Timing Diagram
CLKIN
ADC DIV2
A
0: B = A
1: B = A/2
DLL MULT
B
00: C = B
01: C = B/2
10: C = B/4
CLKOUT2 DIV
C
00: D = C
01: D = C/2
10: D = C/4
INTERP
D
00: E = D
01: E = 2 ؋ D
10: E = 4 ؋ D
E
TxDAC UPDATE RATE
SINGLE CHANNEL
(CANNOT EXCEED
DLL OUTPUT RATE)
REV. 0
ADC SAMPLE RATE
(NOT TO EXCEED 64MHz)
DLL OUTPUT RATE
(NOT TO EXCEED 128MHz)
CLKOUT2
INPUT Tx DATA RATE
(SINGLE CHANNEL)
Figure 10. Single Tx Timing Block Diagram, Alternative Operation
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