AD9860 Datasheet PDF - Analog Devices

AD9860 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9860

Mixed-Signal Front-End (MxFE™) Processor for Broadband Communications

Analog Devices

AD9860 Datasheet PDF : 32 Pages

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AD9860/AD9862

BIT 7: SDIO BiDir (Bidirectional)

Default setting is low, which indicates SPI serial port uses dedi-

cated input and output lines (i.e., 4-wire interface), SDIO and

SDO Pins, respectively. Setting this bit high configures the

serial port to use the SDIO Pin as a bidirectional data pin.

BIT 6: LSB First

Default setting is low, which indicates MSB first SPI Port Access

Mode. Setting this bit high configures the SPI port access to

LSB first mode.

BIT 5: Soft Reset

Writing a high to this register resets all the registers to their

default values and forces the DLL to relock to the input clock.

The Soft Reset Bit is a one shot register and is cleared immediately

after the register write is completed.

high speed applications when clock duty cycle affects noise and

distortion performance the most. This bit should be set high in

conjunction with Clk Dut Enable register bit.

BIT 1: Shared Ref

Setting this bit high forces the dual receive ADCs into a mode

to share their differential references to provide superior gain

matching. When this option is enabled, the REFT of Channel A

and Channel B should be connected together off-chip and the

REFB of both channels should be connected.

BIT 0: Clk Duty

Setting this bit high enables an on-chip duty cycle stabilizer (DCS)

circuit to generate the internal clock for the Rx block. This option

is useful for adjusting for high speed input clocks with skewed

duty cycle. The DCS Mode can be used with ADC sampling

frequencies over 40 MHz.

BIT 7: VREF, diff (Power-Down)

Setting this bit high will power down the ADC’s differential

references (i.e., REFT and REFB).

BIT 6: VREF (Power-Down)

Setting this register bit high will power down the ADC reference

circuit (i.e., VREF).

BIT 5: Rx Digital (Power-Down)

Setting this bit high will power down the digital section of the

receive path of the chip. Typically, any unused digital blocks are

automatically powered down.

BIT 4/3: Rx Channel B/Rx Channel A (Power-Down)

Either ADC or both ADCs can be powered down by setting the

appropriate register bit high. The entire Rx channel is powered

down, including the differential references, input buffer, and the

internal digital block. The bandgap reference remains active for

quick recovery.

BIT 2/1: Buffer B/Buffer A (Power-Down)

Setting either of these bits high will power down the input buffer

circuits for the respective channel. The input buffer should be

powered down when bypassed. By default, these bits are low and

the input buffers are enabled.

BIT 0: All Rx (Power-Down)

Setting this bit high powers down all circuits related to the

receive path.

BIT 4: Three-state

Setting this bit high will force both Rx data output buses, including

the RxSYNC Pin, into a three-state mode.

BIT 3: Rx Retime

The Rx path can use either of the clock outputs, CLKOUT1 or

CLKOUT2, to latch the Rx output data. Since CLKOUT1 and

CLKOUT2 have slight phase offsets, this provides some timing

flexibility with the interface. By default, this bit is low and the

Rx output latches use CLKOUT1. Setting this bit will force the

Rx output latches to use CLKOUT2.

BIT 2: Twos Complement

Default data format for the Rx data is straight binary. Setting this

bit high will generate two’s complement data.

BIT 1: Inv RxSync

When the receive data is multiplexed onto one data port (i.e., Mux

Mode Enabled), the RxSYNC Pin can be used to decode which

channel generated the current output data at the active port.

Default condition is that RxSYNC is high when Channel A is at

the output and is low when Channel B is at the output. Setting

this bit high reverses this synchronization.

BIT 0: Mux Out

Setting this bit high enables the Rx Mux Mode. Default setting

is low, which is Dual Port Mode, (i.e., non Rx Mux Mode). When in

Rx Mux Mode, both Rx channels share the same output data bus,

pins D0A to D9A (for AD9860) or D0A to D11A (for AD9862).

The other Rx output bus (pins D0B to D9B or D0B to D11B)

outputs a low logic.

BIT 7: Bypass Buffer A/Bypass Buffer B

Setting either of these bits high will bypass the respective input buf-

fer circuit. When the buffer is bypassed, the input signal is routed

directly to the switched capacitor SHA input of the RxPGA. When

operating with buffer bypassed, it should be powered down.

BIT 0–4: RxPGA A/RxPGA B

These 5-bit straight binary registers (Bit 0 is the LSB, Bit 4 is the

MSB) provide control for the programmable gain amplifiers in

the dual receive paths. A 0 dB to 20 dB gain range is accom-

plished through a switched capacitor network with fast settling

of a few clock cycles. The step size is approximately 1 dB. The

setting for these registers is hex14.

BIT 3: 2 Channel

Setting this bit low disables the Rx B output data port (pins D0B

to D9B or D11B), forcing the output pins to zero. By default, the

bit is high and both data paths are active.

BIT 2: Keep –ve

This bit selects whether the receive Hilbert filter will filter positive

or negative frequencies, assuming the filter is enabled. By default

this bit is low, which passes positive frequencies. Setting this bit

high will configure the filter to pass negative frequencies.

BIT 1: Hilbert

This bit enables or disables the Hilbert filter in the receive path.

By default, this bit is low, which disables the receive Hilbert filter.

Setting this bit high enables the receive Hilbert filter.

BIT 2: HS (High Speed) Duty Cycle

Setting this bit high optimizes duty cycle of the internal ADC

sampling clock. It is recommended that this bit be set high in

BIT 0: Decimate

This register enables or disables the decimation filters. By default,

the register setting is low and the decimation filter is disabled.

REV. 0

–13–

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