AD9726 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9726

16-Bit, 600+ MSPS D/A Converter

Analog Devices 

Preliminary Technical Data

AD9726

THEORY OF OPERATION

LVDS INPUTS

The AD9726 uses LVDS (Low Voltage Differential Signaling)

digital inputs to enable high speed digital signaling. LVDS

allows the use of a differential signal for optimum noise reject-

tion, and has small signal amplitude for fast speed and lower

power dissipation. Each differential digital input on the AD9726

has an internal 100 Ω resistor for proper load termination. The

LVDS digital data inputs on the AD9726 meet the IEEE reduced

range (RR) specs for common mode input range (875 mV to

1575 mV) with an input differential threshold of ±350 mV.

DATA SYNCHRONIZATION CIRCUITRY

The high speeds at which the LVDS digital interface is designed

to operate require maintaining synchronization of the data

(DB[15:0]+, DB[15:0]–) and data clock (DATACLK_IN+,

DATACLK_IN–) with the DAC clock (CLK+, CLK–). Since the

DAC clock input is not LVDS, the phase relationship between

that clock and the data can vary, and, unless precautions are

taken, data can be corrupted.

The input data must be provided at the same frequency as the

DAC clock from an LVDS source with an accompanying LVDS

data clock. Since the DAC and data clocks are different types,

their phase relationship is difficult to specify.

The AD9726 provides internal circuitry to keep the data from

being corrupted over a wide variation in relative phase. Once

the DAC and data clocks have been established and synchron-

ization has been initiated, the phase between the two clocks can

vary by at least one full clock cycle without loss of data. If the

phase relationship between the clocks varies enough to cause a

possible loss of data, the AD9726 can be resynchronized in

several different ways.

The internal synchronization circuitry in the AD9726 eases this

problem by allowing the phase to vary by at least one full clock

cycle, once synchronization has been established. It does this by

demultiplexing the incoming data stream into four channels,

each containing every fourth data word. Each of these words is

present for four DAC clock cycles. The data is then remulti-

plexed by sampling each channel with the appropriate DAC

clock cycle.

Initial synchronization is established in one of the following

ways:

1. When the RESET pin is asserted, the synchronization logic

is initiated to provide optimal internal timing.

2. If SPI_DIS is not asserted, the synchronization is optimized

by writing setting SYNC_UPD (02h[1]) high.

3. If SPI_DIS is asserted, the synchronization is optimized by

asserting the SYNC_UPD pin.

Once synchronization is established, the AD9726 needs to be

reoptimized only if operating conditions change enough to

affect the relative phase of the DAC and data clocks by more

than one clock cycle. The AD9726 detects when a synchroni-

zation update is necessary, and indicates this need by asserting

SYNCALRM (02h[0]) or SYNC_ALRM high. If SYNCALRM

(02h[0]) or SYNC_ALRM have been asserted, resynchroni-

zation can be accomplished as follows:

1. If the synchronization logic is in automatic mode

(SYNCMAN (02h[2]) = 0), the synchronization logic will

optimize the internal timing as necessary. Two data words

will typically be lost or repeated when an optimization

occurs. If that possibility could cause serious problems,

manual operation may be required.

2. If the synchronization logic is in manual mode

(SYNCMAN (02h[2]) = 1), the logic will indicate the need

for an update by asserting SYNCALRM (02h[0]) high. In

normal operation, a logic high on SYNCALRM (02h[0])

does not mean that data is being lost, but that conditions

are close to the point where data may be lost. Optimization

should be initiated by setting SYNCUPD (02h[1]) high at a

convenient time.

3. Monitoring the synchronization logic state and initiating

an update can be done via package pins by setting SPI_DIS

high and using the SYNC_ALRM and SYNC_UPD pins in

the same way the manual synchronization operation is

described in step 2.

Note that SYNCUPD (02h[1]) or SYNC_UPD can be asserted

at any time to optimize the synchronization, even if

SYNCALRM (02h[0]) or SYNC_ALRM have not indicated that

it is necessary.

If either the data clock or the DAC clock is interrupted for any

reason, a SYNCUPD or SYNC_UPD should be executed to

insure that no subsequent data is lost.

INTERNAL REFERENCE AND FULL-SCALE OUTPUT

CURRENT

The AD9726 contains an internal band gap reference of 1.2 V.

The reference voltage is applied to an external resistor at FSADJ,

and the resultant current is amplified by the reference buffer to

provide the full-scale current for the DAC output. The gain

equation from the internal reference to the DAC output

(assuming the digital inputs are at full scale) is as follows:

IOUTFS = 1.2 × 32/FSADJ

Taking into account the state of the digital inputs, the output

current of IOUTA and IOUTB at any instant in time is:

IOUTA = IOUTFS × (DB15:DB0)/65536

IOUTB = IOUTFS × (1 − DB15:DB0)/65536

Rev. PrD | Page 13 of 16

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