AD9683 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9683 Datasheet PDF : 44 Pages
| |||
Data Sheet
AD9683
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Reg
Addr Reg Addr
(Hex) Name
Bit 7
(MSB)
Bit 6
0x00 SPI port
0
configuration
LSB first
0x01 Chip ID
0x02 Chip grade
0x08 PDWN modes
0x09 Global clock
Reserved
0x0A PLL status
0x0B Clock divide
PLL locked
status
0x0D Test mode
User test mode cycle:
00 = repeat pattern
(user pattern 1, 2, 3, 4, 1,
2, 3, 4, 1, …);
10 = single pattern
(user pattern 1, 2, 3, 4,
then all zeros)
0x10 Customer offset
Bit 5
Bit 4
Soft reset 1
Bit 3
1
Bit 2
Soft reset
Bit 1
LSB first
Bit 0 (LSB)
0
AD9683 8-bit chip ID is 0xC3
Speed grade:
00 = 250 MSPS,
11 = 170 MSPS
Reserved for chip die revision, currently 0x0
External
PDWN
mode:
0=
PDWN is
full
power-
down,
1=
PDWN
puts
device in
standby
JESD204B
standby
mode
(when
external
PDWN is
used):
0=
JESD204B
core is
unaffected,
1=
JESD204B
core is
powered
down
except for
PLL
JESD204B power modes:
00 = normal mode
(power-up);
01 = power-down
mode, PLL off, serializer
off, clocks stopped,
digital held in reset;
10 = standby mode, PLL
on, serializer off, clocks
stopped, digital circuitry
held in reset
ADC power modes:
00 = normal mode
(power-up),
01 = power-down mode,
10 = standby mode,
does not affect JESD204B
digital circuitry
Clock selection:
00 = Nyquist clock,
01 = RF clock divide by 2,
10 = RF clock divide by 4,
11 = clock off
Clock duty
cycle
stabilizer
enable
JESD204B
link is ready
Clock divide phase relative to
the encode clock:
0x0 = 0 input clock cycles delayed,
0x1 = 1 input clock cycles delayed,
0x2 = 2 input clock cycles delayed,
…
0x7 = 7 input clock cycles delayed
Clock divider ratio relative to
the encode clock:
0x00 = divide by 1,
0x01 = divide by 2,
0x02 = divide by 3,
…
0x07 = divide by 8
Long
pseudo-
random
number
generator
reset:
0 = long
PRN
enabled,
1 = long
PRN held
in reset
Short
pseudo-
random
number
generator
reset:
0 = short
PRN
enabled,
1 = short
PRN held in
reset
Data output test generation mode:
0000 = off (normal mode),
0001 = midscale short,
0010 = positive full scale,
0011 = negative full scale,
0100 = alternating checkerboard,
0101 = PN sequence long,
0110 = PN sequence short,
0111 = 1/0 word toggle,
1000 = user test mode (use with Address 0x0D,
Bits[7:6] and user pattern 1, 2, 3, 4),
1001 to 1110 = unused,
1111 = ramp output
Offset adjust in LSBs from +31 to −32 (twos complement format):
01 1111 = adjust output by +31,
01 1110 = adjust output by +30,
…
00 0001 = adjust output by +1,
00 0000 = adjust output by 0 (default),
…
10 0001 = adjust output by −31,
10 0000 = adjust output by −32
Default
0x18
0xC3
0x00
or
0x30
0x00
0x01
0x00
0x00
0x00
Notes
Read only
DCS enabled
if clock divider
enabled
Read only
Clock divide
values other
than 0x00
automatically
cause the DCS
to become
active
Rev. 0 | Page 35 of 44
|
|
Share Link: 