Data Sheet
CS
SCLK
SDIO
tS
tHIGH
tCLK
tLOW
tDS
tDH
BIT N
BIT N + 1
Figure 57. Serial Control Port Timing—Write
AD9520-5
tC
Table 41. Serial Control Port Timing
Parameter
Description
tDS
Setup time between data and rising edge of SCLK
tDH
Hold time between data and rising edge of SCLK
tCLK
Period of the clock
tS
Setup time between the CS falling edge and the SCLK rising edge (start of communication cycle)
tC
Setup time between the SCLK rising edge and the CS rising edge (end of communication cycle)
tHIGH
Minimum period that SCLK should be in a logic high state
tLOW
Minimum period that SCLK should be in a logic low state
tDV
SCLK to valid SDIO and SDO (see Figure 55)
Rev. B | Page 51 of 74