AD9520-5 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9520-5

12 LVPECL/24 CMOS Output Clock Generator

Analog Devices 

AD9520-5

The AD9520-5 features a dc offset option in single-ended

mode. This option is designed to eliminate the risk of the

reference inputs chattering when they are ac-coupled and the

reference clock disappears. When using the reference switchover,

the single-ended reference inputs should be dc-coupled CMOS

levels (with the AD9520 dc offset feature disabled). Alternatively,

the inputs can be ac-coupled and dc offset feature enabled. Keep in

mind, however, that the minimum input amplitude for the

reference inputs is greater when the dc offset is turned on.

Reference switchover can be performed manually or automatically.

Manual switchover is performed either through Register 0x01C

or by using the REF_SEL pin. Manual switchover requires the

presence of a clock on the reference input that is being switched to;

otherwise, the deglitching feature must be disabled in Bit 7 of

Register 0x01C. The reference switching logic fails if this condition

is not met, and the PLL does not reacquire.

Automatic revertive switchover relies on the REFMON pin to

indicate when REF1 disappears. By programming Register 0x01B =

0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed

to be high when REF1 is invalid, which commands the switch to

REF2. When REF1 is valid again, the REFMON pin goes low, and

the part again locks to REF1. The STATUS pin can also be used for

this function, and REF2 can be used as the preferred reference.

A switchover deglitch feature ensures that the PLL does not

receive rising edges that are far out of alignment with the newly

selected reference. For the switchover deglitch feature to work

correctly, the presence of a clock is required on the reference input

that is being switched to. The deglitching feature can also be

disabled (Register 0x01C[7]).

Automatic nonrevertive switching is not supported.

Reference Divider R

The reference inputs are routed to the reference divider, R. R is a

14-bit counter that can be set to any value from 0 to 16,383 by

writing to Register 0x011 and Register 0x012 (both R = 0 and R = 1

give divide-by-1.) The output of the R divider goes to one of the

PFD inputs to be compared with the VCO frequency divided by

the N divider. The frequency applied to the PFD must not exceed

the maximum allowable frequency, which depends on the

antibacklash pulse setting (see Table 2).

The R divider has its own reset. The R divider can be reset using

the shared reset bit of the R, A, and B counters. It can also be

reset by a SYNC operation.

VCO/VCXO Feedback Divider N—P, A, and B

The N divider is a combination of a prescaler, P, and two counters,

A and B. The total divider value is

N = (P × B) + A

where P can be 2, 4, 8, 16, or 32.

Data Sheet

Prescaler

The prescaler of the AD9520-5 allows for two modes of operation:

a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus

(DM) mode where the prescaler divides by P and (P + 1) {2 and

3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler

modes of operation are given in Table 48, Register 0x016[2:0].

Not all modes are available at all frequencies (see Table 2).

When operating the AD9520-5 in dual modulus mode, P/(P + 1),

the equation used to relate the input reference frequency to the

VCO output frequency is

fVCO = (fREF/R) × (P × B + A) = fREF × N/R

However, when operating the prescaler in FD Mode 1, FD Mode 2,

or FD Mode 3, the A counter is not used (A = 0; the divide is a

fixed divide of P = 2, 4, 8, 16, or 32) and the equation simplifies to

fVCO = (fREF/R) × (P × B) = fREF × N/R

By using combinations of DM and FD modes, the AD9520-5

can achieve values of N from 1 to 262,175.

Table 25 shows how a 10 MHz reference input can be locked to

any integer multiple of N.

Note that the same value of N can be derived in different ways,

as illustrated by the case of N = 12. The user can choose a fixed

divide mode of P = 2 with B = 6; use the dual modulus mode of

2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with

A = 0, B = 3.

A and B Counters

The B counter must be ≥3 or bypassed, and unlike the R

counter, A = 0 is actually zero.

When the prescaler is in dual modulus mode, the A counter

must be equal to or less than the B counter.

The maximum input frequency to the A/B counter is reflected

in the maximum prescaler output frequency (~300 MHz) that is

specified in Table 2. This is the prescaler input frequency (external

VCO or CLK) divided by P. For example, a dual modulus mode

of P = 8/9 is not allowed if the external VCO frequency is greater

than 2400 MHz because the frequency going to the A/B counter

is too high.

When the AD9520-5 B counter is bypassed (B = 1), the A counter

should be set to zero, and the overall resulting divide is equal to

the prescaler setting, P. The possible divide ratios in this mode

are 1, 2, 3, 4, 8, 16, and 32.

Although manual reset is not normally required, the A/B counters

have their own reset bit. Alternatively, the A and B counters can be

reset using the shared reset bit of the R, A, and B counters. Note

that these reset bits are not self-clearing.

Rev. B | Page 32 of 74

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