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AD9520-4 データシートの表示(PDF) - Analog Devices

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AD9520-4 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO ADI
Analog Devices ADI
AD9520-4 Datasheet PDF : 84 Pages
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AD9520-4
TIMING CHARACTERISTICS
Table 5.
Parameter
LVPECL OUTPUT RISE/FALL TIMES
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT
For All Divide Values
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS1
LVPECL Outputs That Share the Same Divider
LVPECL Outputs on Different Dividers
All LVPECL Outputs Across Multiple Parts
CMOS OUTPUT RISE/FALL TIMES
Output Rise Time, tRC
Output Fall Time, tFC
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT
For All Divide Values
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS1
CMOS Outputs That Share the Same Divider
All CMOS Outputs on Different Dividers
All CMOS Outputs Across Multiple Parts
OUTPUT SKEW, LVPECL-TO-CMOS OUTPUT1
Output(s) That Share the Same Divider
Output(s) That Are on Different Dividers
Min Typ
130
130
Max Unit
170 ps
170 ps
Test Conditions/Comments
Termination = 50 Ω to VS_DRV − 2 V
20% to 80%, measured differentially (rise/fall
time are independent of VS and are valid for
VS_DRV = 3.3 V and 2.5 V)
80% to 20%, measured differentially (rise/fall
time are independent of VS and are valid for
VS_DRV = 3.3 V and 2.5 V)
850 1050 1280 ps High frequency clock distribution configuration
800 970 1180 ps Clock distribution configuration
1.0
ps/°C
Termination = open
5
16 ps
VS_DRV = 3.3 V
5
20 ps
VS_DRV = 2.5 V
5
45 ps
VS_DRV = 3.3 V
5
60 ps
VS_DRV = 2.5 V
190 ps
VS_DRV = 3.3 V and 2.5 V
Termination = open
750 960 ps
20% to 80%; CLOAD = 10 pF; VS_DRV = 3.3 V
715 890 ps
80% to 20%; CLOAD = 10 pF; VS_DRV = 3.3 V
965 1280 ps
20% to 80%; CLOAD = 10 pF; VS_DRV = 2.5 V
890 1100 ps
80% to 20%; CLOAD = 10 pF; VS_DRV = 2.5 V
Clock distribution configuration
2.1 2.75 3.55 ns
VS_DRV = 3.3 V
3.35
ns
VS_DRV = 2.5 V
2
ps/°C VS_DRV = 3.3 V and 2.5 V
7
85 ps
10 105 ps
10 240 ps
10 285 ps
600 ps
620 ps
1.18 1.76 2.48 ns
1.20 1.78 2.50 ns
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
All settings identical; different logic type
LVPECL to CMOS on same part
LVPECL to CMOS on same part
1 The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
Rev. 0 | Page 8 of 84
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