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AD9520-4 データシートの表示(PDF) - Analog Devices

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AD9520-4 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO ADI
Analog Devices ADI
AD9520-4 Datasheet PDF : 84 Pages
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AD9520-4
Parameter
PHASE OFFSET IN ZERO DELAY
Phase Offset (REF-to-LVPECL Clock Output
Pins) in Internal Zero Delay Mode
Phase Offset (REF-to-LVPECL Clock Output
Pins) in Internal Zero Delay Mode
Phase Offset (REF-to-CLK Input Pins) in
External Zero Delay Mode
Phase Offset (REF-to-CLK Input Pins) in
External Zero Delay Mode
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge Pump/
Phase Frequency Detector (In-Band
Means Within the LBW of the PLL)
@ 500 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
PLL DIGITAL LOCK DETECT WINDOW2
Lock Threshold (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Unlock Threshold (Hysteresis)2
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Min Typ Max
560 1060 1310
−320 +50 +240
140 630 870
−460 −20 +200
−165
−162
−152
−144
−222
3.5
7.5
3.5
7
15
11
Unit Test Conditions/Comments
REF refers to REFIN (REF1)/REFIN (REF2)
ps
When N delay and R delay are bypassed
ps
When N delay = Setting 110 and R delay is bypassed
ps
When N delay and R delay are bypassed
ps
When N delay = Setting 011 and R delay is bypassed
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
ns
ns
ns
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of
the VCO and subtracting 20 log(N) (where N is the value
of the N divider)
Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is an
approximation of the PFD/CP in-band phase noise (in
the flat region) inside the PLL loop bandwidth; when
running closed-loop, the phase noise, as observed at
the VCO output, is increased by 20 log(N); PLL figure of
merit decreases with decreasing slew rate; see Figure 12
Signal available at LD, STATUS, and REFMON pins when
selected by appropriate register settings; lock detect
window settings can be varied by changing the
CPRSET resistor
Selected by 0x017[1:0] and 0x018[4]
(this is the threshold to go from unlock to lock)
0x017[1:0] = 00b, 01b,11b; 0x018[4] = 1b
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
0x017[1:0] = 10b; 0x018[4] = 0b
This is the threshold to go from lock to unlock
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
0x017[1:0] = 10b; 0x018[4] = 0b
1 The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. 0 | Page 6 of 84
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