When the AD9520 is in a PD power-down, the chip is in the
• The PLL is off (asynchronous power-down).
• The VCO is off.
• The CLK input buffer is off, but the CLK input dc bias
circuit is on.
• In differential mode, the reference input buffer is off, but
the dc bias circuit is still on.
• In singled-ended mode, the reference input buffer is off,
but the dc bias circuit is off.
• All dividers are off.
• All CMOS outputs are tristated.
• All LVPECL outputs are in safe off mode.
• The serial control port is active, and the chip responds to
The PLL section of the AD9520 can be selectively powered
down. There are two PLL power-down modes set by
Register 0x010[1:0]: asynchronous and synchronous.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated. In synchronous power-down
mode, the PLL power-down is gated by the charge pump to
prevent unwanted frequency jumps. The device goes into power-
down on the occurrence of the next charge pump event after the
registers are updated.
The distribution section can be powered down by writing
0x230 = 1b, which turns off the bias to the distribution
section. If the LVPECL power-down mode is in normal
operation (0b), it is possible for a low impedance load on that
LVPECL output to draw significant current during this power-
down. If the LVPECL power-down mode is set to 1b, the
LVPECL output is not protected from reverse bias and can be
damaged under certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
into safe power-down mode by individually writing to the
appropriate registers. The register map details the individual
power-down settings for each output. These settings are found
in 0x0F0 to 0x0FD.
Individual Clock Channel Power-Down
Any of the clock distribution channels can be powered down
individually by writing to the appropriate registers. Powering
down a clock channel is similar to powering down an individual
driver, but it saves more power because the dividers are also
powered down. Powering down a clock channel also automatically
powers down the drivers connected to it. The register map
details the individual power-down settings for each output
channel. These settings are found in 0x192, 0x195,
0x198, and 0x19B.
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