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AD9520-4 データシートの表示(PDF) - Analog Devices

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AD9520-4 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO ADI
Analog Devices ADI
AD9520-4 Datasheet PDF : 84 Pages
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SW1B SW1A
R2
200
R1
200
N1
QN1
N2
QN2
OUT
OUT
SW2
4.4mA
Figure 51. LVPECL Output Simplified Equivalent Circuit
CMOS Output Drivers
The user can also individually configure each LVPECL output
as a pair of CMOS outputs, which provides up to 24 CMOS
outputs. When an output is configured as CMOS, the CMOS
Output A and CMOS Output B are automatically turned on. For
a given differential pair, either the CMOS Output A or Output B
can be turned on or off independently. The user can also select
the relative polarity of the CMOS outputs for any combination of
inverting and noninverting (see Register 0x0F0 to Register 0x0FB).
The user can power down each CMOS output as needed to save
power. The CMOS output power-down is individually controlled
by the enable CMOS output register (0x0F0[6:5] to 0x0FB[6:5]).
The CMOS driver is in tristate when it is powered down.
VS_DRV
OUT1/
OUT1
Figure 52. CMOS Equivalent Output Circuit
RESET MODES
The AD9520 has a power-on reset (POR) and several other
ways to apply a reset condition to the chip.
Power-On Reset
During chip power-up, a power-on reset pulse is issued when
VS reaches ~2.6 V (<2.8 V) and restores the chip either to the
setting stored in EEPROM (with the EEPROM pin = 1) or to
the on-chip setting (with the EEPROM pin = 0). At power-on,
the AD9520 also executes a SYNC operation, which brings the
outputs into phase alignment according to the default settings.
It takes ~70 ms for the outputs to begin toggling after the
power-on reset pulse signal is internally generated.
AD9520-4
Hardware Reset via the RESET Pin
RESET, a hard reset (an asynchronous hard reset is executed by
briefly pulling RESET low), restores the chip either to the setting
stored in EEPROM (the EEPROM pin = 1) or to the on-chip
setting (the EEPROM pin = 0). A hard reset also executes a
SYNC operation, which brings the outputs into phase
alignment according to the default settings. When EEPROM is
inactive (the EEPROM pin = 0), it takes ~2 μs for the outputs to
begin toggling after RESET is issued. When EEPROM is active
(the EEPROM pin = 1), it takes ~20 ms for the outputs to toggle
after RESET is brought high.
Soft Reset via the Serial Port
The serial port control register allows for a soft reset by setting
Bit 2 and Bit 5 in Register 0x000. When Bit 5 and Bit 2 are set,
the chip enters a soft reset mode and restores the chip either to
the setting stored in EEPROM (the EEPROM pin = 1) or to the
on-chip setting (the EEPROM pin = 0), except for Register 0x000.
These bits are self-clearing. During the internal reset, the outputs
are held static.
Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via
the Serial Port
The serial port control register allows the chip to be reset to
settings in EEPROM when the EEPROM pin = 1 via 0xB02[1].
This bit is self-clearing. This bit does not have any effect when
EEPROM pin = 0. It takes ~20 ms for the outputs to begin
toggling after soft_EEPROM register is cleared.
POWER-DOWN MODES
Chip Power-Down via PD
The AD9520 can be put into a power-down condition by
pulling the PD pin low. Power-down turns off most of the
functions and currents inside the AD9520. The chip remains in
this power-down state until PD is brought back to logic high.
When taken out of power down mode, the AD9520 returns to
the settings programmed into its registers prior to the power-
down, unless the registers are changed by new programming
while the PD pin is held low.
Powering down the chip shuts down the currents on the chip,
except the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. The LVPECL bias currents are
needed to protect the LVPECL output circuitry from damage that
can be caused by certain termination and load configurations
when tristated. Because this is not a complete power-down, it
can be called sleep mode. The AD9520 contains special circuitry to
prevent runt pulses on the outputs when the chip is entering or
exiting sleep mode.
Rev. 0 | Page 49 of 84
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