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AD9520-4 データシートの表示(PDF) - Analog Devices

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AD9520-4 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO ADI
Analog Devices ADI
AD9520-4 Datasheet PDF : 84 Pages
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AD9520-4
CHANNEL DIVIDER
OUTPUT CLOCKING
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
1
1
2
3
4
5
6
7
8
9 10 11 12 13 14
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
CHANNEL DIVIDER
OUTPUT CLOCKING
INPUT TO CLK
INPUT TO CHANNEL DIVIDER
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
Figure 49. SYNC Timing Pipeline Delay When VCO Divider Is Used—CLK or VCO Is Input
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
Figure 50. SYNC Timing Pipeline Delay When VCO Divider Is Not Used—CLK Input Only
LVPECL Output Drivers
The LVPECL differential voltage (VOD) is selectable (from
~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to
Register 0x0FB. The LVPECL outputs have dedicated pins for
power supply (VS_DRV), allowing a separate power supply to
be used. VS_DRV can be from 2.5 V to 3.3 V.
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
For this reason, the LVPECL outputs have two power-down
modes: total power-down and safe power-down.
In total power-down mode, all output drivers are shut off
simultaneously. This mode must not be used if there is an
external voltage bias network (such as Thevenin equivalent
termination) on the output pins that will cause a dc voltage to
appear at the powered down outputs. However, total power-
down mode is allowed when the LVPECL drivers are terminated
using only pull-down resistors. The total power-down mode is
activated by setting 0x230[1].
The primary power-down mode is the safe power-down mode.
This mode continues to protect the output devices while powered
down. There are three ways to activate safe power-down mode:
individually set the power-down bit for each driver, power down an
individual output channel (all of the drivers associated with that
channel are powered down automatically), and activate sleep mode.
Rev. 0 | Page 48 of 84
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