AD9520-4BCPZ-REEL7 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9520-4BCPZ-REEL7

12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO

Analog Devices 

AD9520-4

Either the internal VCO or the CLK can be selected as the

source for the direct-to-output signal routing. To connect the

LVPECL outputs directly to the internal VCO or CLK, the user

must select the VCO divider as the source to the distribution

section, even if no channel uses it.

Table 32. Routing VCO Divider Input Directly to the Outputs

Register Setting Selection

0x1E1[1:0] = 00b CLK is the source; VCO divider selected

0x1E1[1:0] = 10b VCO is the source; VCO divider selected

0x192[1] = 1b

Direct-to-output OUT0, OUT1, OUT2

0x195[1] = 1b

Direct-to-output OUT3, OUT4, OUT5

0x198[1] = 1b

Direct-to-output OUT6, OUT7, OUT8

0x19B[1] = 1b

Direct-to-output OUT9, OUT10, OUT11

Clock Frequency Division

The total frequency division is a combination of the VCO

divider (when used) and the channel divider. When the VCO

divider is used, the total division from the VCO or CLK to the

output is the product of the VCO divider (1, 2, 3, 4, 5, and 6)

and the division of the channel divider. Table 33 indicates how the

frequency division for a channel is set.

However, when the VCO divider is set to 1, none of the channel

output dividers can be bypassed.

Channel Dividers

A channel divider drives each group of three LVPECL outputs.

There are four channel dividers (0, 1, 2, and 3) driving twelve

LVPECL outputs (OUT0 to OUT11). Table 34 gives the register

locations used for setting the division and other functions of

these dividers. The division is set by the values of M and N. The

divider can be bypassed (equivalent to divide-by-1, divider circuit

is powered down) by setting the bypass bit. The duty-cycle

correction can be enabled or disabled according to the setting of

the disable div DCC bits.

Table 34. Setting DX for the Output Dividers

Low

Divider Cycles M

High

Cycles N

Bypass

0

0x190[7:4] 0x190[3:0] 0x191[7]

1

0x193[7:4] 0x193[3:0] 0x194[7]

2

0x196[7:4] 0x196[3:0] 0x197[7]

3

0x199[7:4] 0x199[3:0] 0x19A[7]

Disable

Div DCC

0x192[0]

0x195[0]

0x198[0]

0x19B[0]

Channel Frequency Division (0, 1, 2, and 3)

Table 33. Frequency Division

CLK or VCO

Selected

VCO

Divider

Setting1

Channel

Divider

Setting

CLK or VCO 1 to 6

input

Don’t

care

CLK or VCO 1 to 6

input

2 to 32

CLK or VCO 2 to 6

input

Bypass

CLK or VCO 1

input

Bypass

CLK (internal VCO Divider Bypass

VCO off)

Bypassed

CLK (internal VCO Divider 2 to 32

VCO off)

Bypassed

Direct to

Output

Setting

Enable

Disable

Disable

Disable

Don’t

care

Don’t

care

Resulting

Frequency

Division

1

(1 to 6) ×

(2 to 32)

(2 to 6) × (1)

Output static

(illegal state)

1

2 to 32

1 The bypass VCO divider (0x1E1[0] = 1) is not the same as VCO divider = 1.

The channel dividers feeding the output drivers contain one 2-

to-32 frequency divider. This divider provides for division-by-1

to division-by-32. Division-by-1 is accomplished by bypassing

the divider. The dividers also provide for a programmable duty

cycle, with optional duty-cycle correction when the divide ratio

is odd. A phase offset or delay in increments of the input clock

cycle is selectable. The channel dividers operate with a signal at

their inputs up to 1600 MHz. The features and settings of the

dividers are selected by programming the appropriate setup

and control registers (see Table 49 through Table 60).

VCO Divider

The VCO divider provides frequency division between the

internal VCO or the external CLK input and the clock

distribution channel dividers. The VCO divider can be set

to divide by 1, 2, 3, 4, 5, or 6 (see Table 56, 0x1E0[2:0]).

For each channel (where the channel number is x: 0, 1, 2, or 3),

the frequency division, DX, is set by the values of M and N

(four bits each, representing Decimal 0 to Decimal 15), where

Number of Low Cycles = M + 1

Number of High Cycles = N + 1

The cycles are cycles of the clock signal currently routed to the

input of the channel dividers (VCO divider out or CLK).

When a divider is bypassed, DX = 1.

Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows

each channel divider to divide by any integer from 1 to 32.

Duty Cycle and Duty-Cycle Correction

The duty cycle of the clock signal at the output of a channel is a

result of some or all of the following conditions:

• The M and N values for the channel

• DCC enabled/disabled

• VCO divider enabled/bypassed

• The CLK input duty cycle (note that the internal VCO has a

50% duty cycle)

The DCC function is enabled by default for each channel divider.

However, the DCC function can be disabled individually for

each channel divider by setting the disable divider DCC bit for

that channel.

Certain M and N values for a channel divider result in a non-

50% duty cycle. A non-50% duty cycle can also result with an

even division, if M ≠ N. The duty-cycle correction function

automatically corrects non-50% duty cycles at the channel

divider output to 50% duty cycle.

Rev. 0 | Page 45 of 84

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