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AD9520-4 データシートの表示(PDF) - Analog Devices

部品番号コンポーネント説明メーカー
AD9520-4 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO ADI
Analog Devices ADI
AD9520-4 Datasheet PDF : 84 Pages
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AD9520-4
After leaving holdover, the loop then reacquires lock and the
LD pin must charge (if 0x01D[3] = 1) before it can reenter
holdover (CP high impedance).
The holdover function always responds to the state of the
currently selected reference (0x01C). If the loop loses lock
during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
The following registers affect the automatic/internal holdover
function:
0x018[6:5]—lock detect counter. This changes how many
consecutive PFD cycles with edges inside the lock detect
window are required for the DLD indicator to indicate lock.
This impacts the time required before the LD pin can begin
to charge as well as the delay from the end of a holdover
event until the holdover function can be re-engaged.
0x018[3]—disable digital lock detect. This bit must be set to a
0 to enable the DLD circuit. Internal/automatic holdover does
not operate correctly without the DLD function enabled.
0x01A[5:0]—lock detect pin control. Set this to 000100b to
put it in the current source lock detect mode if using the LD
pin comparator. Load the LD pin with a capacitor of an
appropriate value.
0x01D[3]—LD pin comparator enable. 1 = enable; 0 =
disable. When disabled, the holdover function always senses
the LD pin as high.
0x01D[1]—external holdover control.
0x01D[0]—holdover enable and ignore reference frequency
status. If holdover is disabled, both external and
automatic/internal holdover are disabled.
For example, to use automatic holdover with
Automatic reference switchover, prefer REF1.
Digital lock detect: five PFD cycles, high range window.
Automatic holdover using the LD pin comparator.
The following registers are set (in addition to the normal PLL
registers):
0x018[6:5] = 00b; lock detect counter = five cycles.
0x018[4] = 0b; digital lock detect window = high range.
0x018[3] = 0b; disable DLD normal operation.
0x01A[5:0] = 000100b; program LD pin control to current
source lock detect mode.
0x01C[4] = 1b; enable automatic switchover.
0x01C[3] = 0b; prefer REF1.
0x01C[2:1] = 11b; enable REF1 and REF2 input buffers.
0x01D[3] = 1b; enable LD pin comparator.
0x01D[1] = 0b; disable external holdover mode and use
automatic/internal holdover mode.
0x01D[0] = 1b; enable holdover.
Frequency Status Monitors
The AD9520 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is
shown in Figure 45.
The PLL reference monitors have two threshold frequencies:
normal and extended (see Table 17). The reference frequency
monitor thresholds are selected in 0x01F.
REF_SEL
VS GND
RSET
REFMON
OPTIONAL
REFIN
REFIN
BYPASS
LF
REF1
REFERENCE
SWITCHOVER
REF2
STATUS
STATUS
BUF
LOW DROPOUT
REGULATOR (LDO)
DISTRIBUTION
REFERENCE
VCO STATUS
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
ZERO DELAY BLOCK
PROGRAMMABLE
N DELAY
CPRSET VCP
LOCK
DETECT
HOLD
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CLK
CLK
DIVIDE BY 1,
2, 3, 4, 5, OR 6
FROM CHANNEL
DIVIDER 0
10
Figure 45. Reference and VCO Status Monitors
Rev. 0 | Page 41 of 84
LD
CP
STATUS
VS_DRV
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