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# AD9520-4 データシートの表示（PDF） - Analog Devices

 部品番号 コンポーネント説明 メーカー AD9520-4 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO Analog Devices AD9520-4 Datasheet PDF : 84 Pages
 First Prev 31 32 33 34 35 36 37 38 39 40 Next Last Prescaler
The prescaler of the AD9520 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3 and a dual modulus (DM)
mode where the prescaler divides by P and (P + 1) {2 and 3, 4
and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes of
operation are given in Table 53, 0x016[2:0]. Not all modes are
available at all frequencies (see Table 2).
When operating the AD9520 in dual modulus mode, P/(P + 1),
the equation used to relate the input reference frequency to the
VCO output frequency is
fVCO = (fREF/R) × (P × B + A) = fREF × N/R
However, when operating the prescaler in FD mode 1, 2, or 3,
the A counter is not used (A = 0) and the equation simplifies to
fVCO = (fREF/R) × (P × B) = fREF × N/R
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32.
By using combinations of DM and FD modes, the AD9520 can
achieve values of N all the way down to N = 1. Table 29 shows
how a 10 MHz reference input can be locked to any integer
multiple of N.
Note that the same value of N can be derived in different ways,
as illustrated by the case of N = 12. The user can choose a fixed
divide mode P = 2 with B = 6, use the dual modulus mode 2/3
with A = 0, B = 6, or use the dual modulus mode 4/5 with
A = 0, B = 3.
A and B Counters
The AD9520 B counter can be bypassed (B = 1). This B counter
bypass mode is only valid when using the prescaler in FD mode.
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32.
Unlike the R counter, an A = 0 is actually zero. The B counter
must be ≥3 or bypassed.
The maximum input frequency to the A/B counter is reflected
in the maximum prescaler output frequency (~300 MHz) specified
in Table 2. This is the prescaler input frequency (VCO or CLK)
divided by P.
Although manual reset is not normally required, the A/B counters
have their own reset bit. The A and B counters can be reset using
the shared reset bit of the R, A, and B counters. They can also
be reset through a SYNC operation.
R, A, and B Counters: SYNC Pin Reset
The R, A, and B counters can also be reset simultaneously
through the SYNC pin. This function is controlled by 0x019[7:6]
(see Table 53). The SYNC pin reset is disabled by default.
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays can be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See 0x019 in Table 53.
Table 29. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N
fREF (MHz) R P A B N
fVCO (MHz)
Mode
Notes
10
1 1 X1 1 1
10
FD
P = 1, B = 1 (bypassed)
10
1 2 X1 1 2
20
FD
P = 2, B = 1 (bypassed)
10
1 1 X1 3 3
30
FD
P = 1, B = 3
10
1 1 X1 4 4
40
FD
P = 1, B = 4
10
1 1 X1 5 5
50
FD
P = 1, B = 5
10
1 2 X1 3 6
60
FD
P = 2, B = 3
10
120 36
60
DM
P and P + 1 = 2 and 3, A = 0, B = 3
10
121 37
70
DM
P and P + 1 = 2 and 3, A = 1, B = 3
10
122 38
80
DM
P and P + 1 = 2 and 3, A = 2, B = 3
10
121 49
90
DM
P and P + 1 = 2 and 3, A = 1, B = 4
10
1
2
X1 5
10
100
FD
P = 2, B = 5
10
1 2 0 5 10 100
DM
P and P + 1 = 2 and 3, A = 0, B = 5
10
1 2 1 5 11 110
DM
P and P + 1 = 2 and 3, A = 1, B = 5
10
1
2
X1 6
12
120
FD
P = 2, B = 6
10
1 2 0 6 12 120
DM
P and P + 1 = 2 and 3, A = 0, B = 6
10
1 4 0 3 12 120
DM
P and P + 1 = 4 and 5, A = 0, B = 3
10
1 4 1 3 13 130
DM
P and P + 1 = 4 and 5, A = 1, B = 3
1 X = don’t care.
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