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AD9520-4 データシートの表示(PDF) - Analog Devices

AD9520-4 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO ADI
Analog Devices ADI
AD9520-4 Datasheet PDF : 84 Pages
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The AD9520 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 49 to Table 60). Each section or function must be
individually programmed by setting the appropriate bits in the
corresponding control register or registers. Once the desired
configuration is programmed, the user can store these values in
the on-board EEPROM to allow the part to powerup in the desired
configuration without user intervention.
Mode 0: Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must
be employed to ensure that the frequency presented to the channel
dividers does not exceed its specified maximum frequency (see
Table 3). The internal PLL uses an external loop filter to set the
loop bandwidth. The external loop filter is also crucial to the
loop stability.
When using the internal VCO, it is necessary to calibrate the
VCO (0x018[0]) to ensure optimal performance.
For internal VCO and clock distribution applications, the
register settings shown in Table 22 should be used.
Table 22. Settings When Using Internal VCO
0x010[1:0] = 00b PLL normal operation (PLL on)
0x010 to 0x01E
PLL settings; select and enable a reference
input; set R, N (P, A, B), PFD polarity, and ICP
according to the intended loop configuration
0x1E1[1] = 1b
VCO selected as the source
Enable reference inputs
Set VCO divider
0x1E1[0] = 0b
Use the VCO divider as source for
distribution section
0x018[0] = 0
0x232[0] = 1
Reset VCO calibration and issue IO_UPDATE
(not necessary for first time after power-up,
but must be done subsequently)
0x018[0] = 1,
0x232[0] = 1
Initiate VCO calibration, Issue IO_UPDATE
Rev. 0 | Page 28 of 84
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