AD9520-4 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9520-4

12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO

Analog Devices 

AD9520-4

POWER DISSIPATION

Table 18.

Parameter

Min Typ Max Unit Test Conditions/Comments

POWER DISSIPATION, CHIP

Does not include power dissipated in external resistors; all

LVPECL outputs terminated with 50 Ω to VCC − 2 V; all CMOS

outputs have 10 pF capacitive loading; VS_DRV = 3.3 V

Power-On Default

1.32 1.5 W No clock; no programming; default register values

PLL Locked; One LVPECL Output Enabled

0.55 0.64 W

fREF = 25 MHz; fOUT = 250 MHz; VCO = 1.5 GHz; VCO divider = 2;

one LVPECL output and output divider enabled; zero delay off;

ICP = 4.8 mA

PLL Locked; One CMOS Output Enabled

0.52 0.62 W

fREF = 25 MHz; fOUT = 62.5 MHz; VCO = 1.5 GHz; VCO divider = 2;

one CMOS output and output divider enabled; zero delay off;

ICP = 4.8 mA

Distribution Only Mode; VCO Divider On;

One LVPECL Output Enabled

0.39 0.46 W

fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider = 2; one LVPECL

output and output divider enabled; zero delay off

Distribution Only Mode; VCO Divider Off;

One LVPECL Output Enabled

0.36 0.42 W

fCLK = 1.6 GHz; fOUT = 200 MHz; VCO divider bypassed; one

LVPECL output and output divider enabled; zero delay off

Maximum Power, Full Operation

1.5 1.7 W

PLL on; internal VCO = 160 MHz; VCO divider = 2; all channel

dividers on; 12 LVPECL outputs @ 125 MHz; zero delay on

PD Power-Down

60 80 mW PD pin pulled low; does not include power dissipated in

terminations

PD Power-Down, Maximum Sleep

24 33 mW PD pin pulled low; PLL power-down 0x010[1:0] = 01b; SYNC

power-down 0x230[2] = 1b; power-down distribution reference

0x230[1] = 1b

VCP Supply

4 4.8 mW PLL operating; typical closed-loop configuration

POWER DELTAS, INDIVIDUAL FUNCTIONS

Power delta when a function is enabled/disabled

VCO Divider On/Off

32 40 mW VCO divider not used

REFIN (Differential) Off

25 30 mW Delta between reference input off and differential reference

input mode

REF1, REF2 (Single-Ended) On/Off

15 20 mW Delta between reference inputs off and one singled-ended

reference enabled; double this number if both REF1 and REF2

are both powered up

VCO On/Off

67 104 mW Internal VCO disabled; CLK input selected

PLL Dividers and Phase Detector On/Off

51 63 mW PLL off to PLL on, normal operation; no reference enabled

LVPECL Channel

121 144 mW No LVPECL output on to one LVPECL output on; channel divider

set to 1

LVPECL Driver

51 73 mW Second LVPECL output turned on, same channel

CMOS Channel

145 180 mW No CMOS output on to one CMOS output on; channel divider

set to 1; fOUT = 62.5 MHz and 10 pF of capacitive loading

CMOS Driver On/Off

11 24 mW Additional CMOS outputs within the same channel turned on

Channel Divider Enabled

40 57 mW Delta between divider bypassed (divide-by-1) and divide-by-2 to

divide-by-32

Zero Delay Block On/Off

30 34 mW

Rev. 0 | Page 16 of 84

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