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AD9520-4 データシートの表示(PDF) - Analog Devices

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AD9520-4 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO ADI
Analog Devices ADI
AD9520-4 Datasheet PDF : 84 Pages
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AD9520-4
SERIAL CONTROL PORT—I²C MODE
Table 14.
Parameter
SDA, SCL (WHEN INPUTS)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Current with an Input Voltage Between
0.1 VS and 0.9 VS
Hysteresis of Schmitt Trigger Inputs
Pulse width of Spikes That Must Be Suppressed by the
Input Filter, tSP
SDA (WHEN OUTPUTTING DATA)
Output Logic 0 Voltage at 3 mA Sink Current
Output Fall Time from VIHMIN to VILMAX with a Bus
Capacitance from 10 pF to 400 pF
TIMING
Clock Rate (SCL, fI2C)
Bus Free Time Between a Stop and Start Condition, tIDLE
Setup Time for a Repeated Start Condition, tSET; STR
Hold Time (Repeated) Start Condition (After This Period,
the First Clock Pulse Is Generated, tHLD; STR)
Setup Time for Stop Condition, tSET; STP
Low Period of the SCL Clock, tLOW
High Period of the SCL Clock, tHIGH
SCL, SDA Rise Time, tRISE
SCL, SDA Fall Time, tFALL
Data Setup Time, tSET; DAT
Data Hold Time, tHLD; DAT
Capacitive Load for Each Bus Line, Cb
Min
0.7 × VS
−10
0.015 × VS
Typ Max Unit Test Conditions/Comments
V
0.3 × VS V
+10
μA
50
ns
20 + 0.1 Cb (Cb =
capacitance of
one bus line in pF)
1.3
0.6
0.6
0.6
1.3
0.6
20 + 0.1 Cb
20 + 0.1 Cb
120
140
0.4
V
250
ns
Note that all I2C timing values
referred to VIHMIN (0.3 × VS) and
VILMAX levels (0.7 × VS)
400
kHz
μs
μs
μs
μs
μs
μs
300
ns
300
ns
ns This is a minor deviation from
the original I²C specification of
100 ns minimum
880
ns This is a minor deviation from
the original I²C specification of
0 ns minimum1
400
pF
1 According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL
falling edge.
Rev. 0 | Page 14 of 84
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