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AD9520-4 データシートの表示(PDF) - Analog Devices

部品番号コンポーネント説明メーカー
AD9520-4 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO ADI
Analog Devices ADI
AD9520-4 Datasheet PDF : 84 Pages
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AD9520-4
CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter
LVPECL ABSOLUTE PHASE NOISE
Min Typ
Max Unit
VCO = 1.8 GHz; OUTPUT = 1.8 GHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
VCO = 1.625 GHz; OUTPUT = 1.625 GHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
VCO = 1.45 GHz; OUTPUT = 1.45 GHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
−54
−84
−108
−128
−143
−148
−58
−87
−111
−130
−144
−148
−62
−91
−115
−133
−143
−148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
Internal VCO; direct-to-LVPECL output and for
loop bandwidths < 1 kHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
VCO = 1.475 GHz; LVPECL = 245.76 MHz; PLL LBW = 39 kHz
VCO = 1.475 GHz; LVPECL = 122.88 MHz; PLL LBW = 39 kHz
VCO = 1.475 GHz; LVPECL = 61.44 MHz; PLL LBW = 39 kHz
Min Typ Max Unit Test Conditions/Comments
Application example based on a typical
setup where the reference source is
clean, so a wider PLL loop bandwidth is
used; reference = 15.36 MHz; R = 1
109
fS rms Integration BW = 200 kHz to 10 MHz
269
fS rms Integration BW = 12 kHz to 20 MHz
114
fS rms Integration BW = 200 kHz to 10 MHz
263
fS rms Integration BW = 12 kHz to 20 MHz
146
fS rms Integration BW = 200 kHz to 10 MHz
291
fS rms Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
VCO = 1.555 GHz; LVPECL = 155.52 MHz; PLL LBW = 1.8 kHz
VCO = 1.474 GHz; LVPECL = 122.88 MHz; PLL LBW = 1.9 kHz
Min Typ Max Unit Test Conditions/Comments
Application example based on a typical
setup where the reference source is
jittery, so a narrower PLL loop bandwidth
is used; reference = 10.0 MHz; R = 20
440
fS rms Integration BW = 12 kHz to 20 MHz
360
fS rms Integration BW = 12 kHz to 20 MHz
Rev. 0 | Page 11 of 84
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