AD9520-2 View Datasheet(PDF) - Analog Devices
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AD9520-2 Datasheet PDF : 84 Pages
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AD9520-2
SPECIFICATIONS
Typical (typ) is given for VS = VS_DRV = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise
noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
VS
VS_DRV
VCP
RSET Pin Resistor
CPRSET Pin Resistor
BYPASS Pin Capacitor
Min Typ Max Unit Test Conditions/Comments
3.135 3.3 3.465 V 3.3 V ± 5%
2.375
VS V This is nominally 2.5 V to 3.3 V ± 5%
VS
5.25 V This is nominally 3.3 V to 5.0 V ± 5%
4.12
kΩ Sets internal biasing currents; connect to ground
5.1
kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);
actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground
220
nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
Frequency Range
VCO Gain (KVCO)
Tuning Voltage (VT)
Frequency Pushing (Open-Loop)
Phase Noise @ 1 kHz Offset
Phase Noise @ 100 kHz Offset
Phase Noise @ 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
with DC Offset Off )
Input Frequency (AC-Coupled
with DC Offset On)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled
with DC Offset Off )
Input Sensitivity (AC-Coupled
with DC Offset On)
Input Logic High, DC Offset Off
Input Logic Low, DC Offset Off
Input Current
Input Capacitance
Min Typ Max Unit Test Conditions/Comments
2020
0.5
38
1
−52
−108
−128
2335
VCP −
0.5
MHz
MHz/V
V
MHz/V
dBc/Hz
dBc/Hz
dBc/Hz
See Figure 13
See Figure 8
VCP ≤ VS when using internal VCO
f = 2175 MHz
f = 2175 MHz
f = 2175 MHz
Differential mode (can accommodate single-ended
input by ac grounding undriven input)
0
250 MHz Frequencies below about 1 MHz should be dc-coupled;
be careful to match VCM (self-bias voltage)
280
mV p-p
1.34 1.60 1.75 V
Self-bias voltage of REFIN1
1.30 1.50 1.60 V
Self-bias voltage of REFIN1
4.0 4.8 5.9 kΩ
Self-biased1
4.4 5.3 6.4 kΩ
Self-biased1
Two single-ended CMOS-compatible inputs
10
250 MHz Slew rate must be > 50 V/μs
250 MHz
Slew rate must be > 50 V/μs, and input amplitude
sensitivity specification must be met; see input sensitivity
0
250 MHz Slew rate > 50 V/μs; CMOS levels
0.55
3.28 V p-p VIH should not exceed VS
1.5
2.78 V p-p VIH should not exceed VS
2.0
−100
2
V
0.8 V
+100 μA
pF
Each pin, REFIN (REF1)/REFIN (REF2)
Rev. 0 | Page 4 of 84
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