AD9520-2 Datasheet PDF - Analog Devices

AD9520-2 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9520-2

12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO

Analog Devices

AD9520-2 Datasheet PDF : 84 Pages

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AD9520-2

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)

Table 7.

Parameter

LVPECL ABSOLUTE PHASE NOISE

Min Typ Max Unit

VCO = 2.335 GHz; Output = 2.335 GHz

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

@ 10 MHz Offset

@ 40 MHz Offset

VCO = 2.175 GHz; Output = 2.175 GHz

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

@ 10 MHz Offset

@ 40 MHz Offset

VCO = 2.05 GHz; Output = 2.05 GHz

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

@ 10 MHz Offset

@ 40 MHz Offset

−49

−80

−105

−125

−140

−146

−52

−83

−108

−128

−142

−147

−55

−84

−110

−130

−142

−147

dBc/Hz

Test Conditions/Comments

Internal VCO; direct-to-LVPECL output and for

loop bandwidths < 1 kHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)

Table 8.

Parameter

LVPECL OUTPUT ABSOLUTE TIME JITTER

VCO = 2.212 GHz; LVPECL = 245.76 MHz; PLL LBW = 66 kHz

VCO = 2.212 GHz; LVPECL = 122.88 MHz; PLL LBW = 66 kHz

VCO = 2.212 GHz; LVPECL = 61.44 MHz; PLL LBW = 66 kHz

Min Typ Max Unit Test Conditions/Comments

Application example based on a typical

setup where the reference source is

clean, so a wider PLL loop bandwidth is

used; reference = 15.36 MHz; R DIV = 1

145

fs rms Integration BW = 200 kHz to 10 MHz

321

fs rms Integration BW = 12 kHz to 20 MHz

155

fs rms Integration BW = 200 kHz to 10 MHz

324

fs rms Integration BW = 12 kHz to 20 MHz

169

fs rms Integration BW = 200 kHz to 10 MHz

336

fs rms Integration BW = 12 kHz to 20 MHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)

Table 9.

Parameter

LVPECL OUTPUT ABSOLUTE TIME JITTER

VCO = 2.177 GHz; LVPECL = 155.52 MHz; PLL LBW = 2.1 kHz

VCO = 2.212 GHz; LVPECL = 122.88 MHz; PLL LBW = 2.2 kHz

Min Typ Max Unit Test Conditions/Comments

Application example based on a typical

setup where the reference source is

jittery, so a narrower PLL loop bandwidth

is used; reference = 19.44 MHz; R DIV = 162

569

fs rms Integration BW = 12 kHz to 20 MHz

599

fs rms Integration BW = 12 kHz to 20 MHz

Rev. 0 | Page 11 of 84

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