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AD9648 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD9648 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter ADI
Analog Devices ADI
AD9648 Datasheet PDF : 44 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD9648
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
CMOS Mode (DRVDD = 1.8 V)
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)2
DCO to Data Skew (tSKEW)
LVDS Mode (DRVDD = 1.8 V)
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)2
DCO to Data Skew (tSKEW)
CMOS Mode Pipeline Delay (Latency)
LVDS Mode Pipeline Delay (Latency) Channel A/Channel B
Wake-Up Time (Power Down)3
Wake-Up Time (Standby)
Out-of-Range Recovery Time
AD9648-105
AD9648-125
Temp Min Typ
Max Min Typ
Max Unit
Full
1000
1000 MHz
Full 20
Full 10
Full
9.52
Full
4.76
Full
1.0
Full
0.07
105 20
105 10
8
4
1.0
0.07
125 MSPS
125 MSPS
ns
ns
ns
ps rms
Full 1.8 2.9
Full 2.0 3.1
Full −1.2 −0.1
4.4 1.8 2.9
4.4 2.0 3.1
+1.0 −1.2 −0.1
4.4 ns
4.4 ns
+1.0 ns
Full
2.4
2.4
ns
Full
2.4
2.4
ns
Full −0.20 +0.03 +0.25 −0.20 +0.03 +0.25 ns
Full
16
16
Cycles
Full
16/16.5
16/16.5
Cycles
Full
350
350
µs
Full
250
250
ns
Full
2
2
Cycles
1 Conversion rate is the clock rate after the divider.
2 Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see Table 18).
3 Wake-up time is defined as the time required to return to normal operation from power-down mode.
Rev. 0 | Page 8 of 44
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