User I/O Control 2 (Register 0x101)
Bit 7—OEB Pin Enable
If the OEB pin enable bit (Bit 7) is set, the OEB pin is enabled.
If Bit 7 is clear, the OEB pin is disabled (default).
Bit 0—SDIO Pull-Down
Bit 0 can be set to disable the internal 30 kΩ pull-down on the
SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.
User I/O Control 3 (Register 0x102)
Bit 3—VCM Power-Down
Bit 3 can be set high to power down the internal VCM
generator. This feature is used when applying an external
Rev. 0 | Page 40 of 44