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AD9648 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD9648 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter ADI
Analog Devices ADI
AD9648 Datasheet PDF : 44 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
AD9648
Addr
(Hex)
0x0B
0x0C
0x0D
0x0E
0x10
0x14
0x15
0x16
0x17
Register
Name
Clock
divide
(global)
Bit 7
(MSB)
Open
Bit 6
Open
Bit 5
Open
Bit 4
Open
Enhance-
ment
control
(global)
Open
Open
Open
Open
Bit 3
Open
Open
Bit 2
Bit 1
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Chop
0=
disabled
1=
enabled
Open
Bit 0
(LSB)
Open
Default
Value
(Hex)
0x00
Comments
The divide
ratio is
value plus 1
0x00
Chop mode
enabled if
Bit 2 is
enabled
Test mode
(local)
BIST
enable
(global)
Customer
offset
adjust
(local)
Output
mode
Output
adjust
Clock
phase
control
(global)
Output
delay
(global)
User test mode control
00 = single pattern mode
01 = alternate
continuous/repeat
pattern mode
10 = single once pattern
mode
11 = alternate once
pattern mode
Open
Open
Output port logic type
(global)
00 = CMOS, 1.8 V
10 = LVDS, ANSI
11 = LVDS, reduced
range
Open
Open
Invert
DCO
clock
0 = not
inverted
1=
inverted
Open
DCO
clock
delay
0=
disabled
1=
enabled
Open
Reset PN
long gen
Reset PN
short gen
Output test mode
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN long sequence
0110 = PN short sequence
0111 = one/zero word toggle
1000 = user test mode
1111 = ramp output
Open
Open
Open
Initialize
BIST
sequence
Open
BIST enable
Offset adjust in LSBs from +127 to −128
(twos complement format)
Output
Interleave
enable
(global)
Output port
disable (local)
Open
(global)
Output
invert
(local)
Output format
00 = offset binary
01 = twos complement
10 = Gray code
CMOS 1.8 V DCO drive
strength
00 = 1×
01 = 2×
10 = 3×
11 = 4×
Open
Open
Open
Open
Data delay
0=
disabled
1=
enabled
Open
Open
Open
CMOS 1.8 V data
drive strength
00 = 1×
01 = 2×
10 = 3×
11 = 4×
Input clock divider phase adjust
relative to the encode clock
000 = no delay
001 = one input clock cycle
010 = two input clock cycles
011 = three input clock cycles
100 = four input clock cycles
101 = five input clock cycles
110 = six input clock cycles
111 = seven input clock cycles
Delay selection
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
0x00
0x00
0x00
0x00
0x00
0x00
0x00
When this
register is
set, the test
data is
placed on
the output
pins in
place of
normal data
Configures
the
outputs
and the
format of
the data
Determines
CMOS
output
drive
strength
properties
Allows
selection of
clock
delays into
the input
clock
divider
This sets
the fine
output
delay of
the output
clock but
does not
change
internal
timing
Rev. 0 | Page 37 of 44
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