If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 55. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer
excellent jitter performance.
0.1µF PECL DRIVER
Figure 55. Differential PECL Sample Clock (Up to 1 GHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 56. The AD9510/
clock drivers offer excellent jitter performance.
0.1µF LVDS DRIVER
Figure 56. Differential LVDS Sample Clock (Up to 1 GHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
150Ω RESISTOR IS OPTIONAL.
Figure 57. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Input Clock Divider
The AD9648 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
The AD9648 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the
clock divider to be resynchronized on every SYNC signal or
only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
The AD9648 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9648. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure 58.
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 µs to 5 µs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
SNR (DCS ON)
SNR (DCS OFF)
POSITIVE DUTY CYCLE (%)
Figure 58. SNR vs. DCS On/Off
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