External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 51 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
VREF ERROR (mV)
Figure 51. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 41). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9648 sample clock
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 52) and require no external bias.
Clock Input Options
The AD9648 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern, as described in the Jitter Considerations
Figure 53 and Figure 54 show two preferred methods for clock-
ing the AD9648 (at clock rates up to 1 GHz prior to internal CLK
divider). A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF
transformer or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 1 GHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9648 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9648 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
ADT1-1WT, 1:1 Z
Figure 53. Transformer-Coupled Differential Clock (Up to 200 MHz)
Figure 54. Balun-Coupled Differential Clock (Up to 1 GHz)
Figure 52. Equivalent Clock Input Circuit
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