THEORY OF OPERATION
The AD9648 dual ADC design can be used for diversity
reception of signals, where the ADCs are operating identically
on the same carrier but from two separate antennae. The ADCs
can also be operated with independent analog inputs. The user
can sample any fS/2 frequency segment from dc to 200 MHz,
using appropriate low-pass or band-pass filtering at the ADC
inputs with little loss in ADC performance. Operation to
300 MHz analog input is permitted but occurs at the expense
of increased ADC noise and distortion.
In nondiversity applications, the AD9648 can be used as a base-
band or direct downconversion receiver, where one ADC is
used for I input data and the other is used for Q input data.
Synchronization capability is provided to allow synchronized
timing between multiple channels or multiple devices.
Programming and control of the AD9648 is accomplished using
a 3-bit SPI-compatible serial interface.
The AD9648 architecture consists of a multistage, pipelined ADC.
Each stage provides sufficient overlap to correct for flash errors in
the preceding stage. The quantized outputs from each stage are
combined into a final 14-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate with a
new input sample while the remaining stages operate with
preceding samples. Sampling occurs on the rising edge of
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the CMOS/LVDS output buffers. The output
buffers are powered from a separate (DRVDD) supply, allowing
digital output noise to be separated from the analog core. During
power-down, the output buffers go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9648 is a differential switched-
capacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
Figure 42. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample-and-hold mode (see Figure 42). When the input circuit
is switched to sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current injected from the output
stage of the driving source. In addition, low Q inductors or ferrite
beads can be placed on each leg of the input to reduce high
differential capacitance at the analog inputs and, therefore,
achieve the maximum bandwidth of the ADC. Such use of low
Q inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Either a shunt capacitor or two
single-ended capacitors can be placed on the inputs to provide a
matching passive network. This ultimately creates a low-pass
filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, the AN-827 Application Note, and the
Analog Dialogue article “Transformer-Coupled Front-End for
Wideband A/D Converters” (Volume 39, April 2005) for more
information. In general, the precise values depend on the
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