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AD9148-EBZ View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
AD9148-EBZ Datasheet PDF : 72 Pages
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AD9148
Data Sheet
INPUT/OUTPUT SIGNAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL (SCLK, SDIO, CS, RESET, TMS, TDI, TCK)
Input VIN Logic High (IOVDD = 1.8 V)
Input VIN Logic High (IOVDD = 3.3 V)
Input VIN Logic Low (IOVDD = 1.8 V)
Input VIN Logic Low (IOVDD = 3.3 V)
CMOS OUTPUT LOGIC LEVEL (SDIO, SDO, IRQ, PLL_LOCK, TDO)
Output VOUT Logic High (IOVDD = 1.8 V)
Output VOUT Logic High (IOVDD = 3.3 V)
Output VOUT Logic Low (IOVDD = 1.8 V)
Output VOUT Logic Low (IOVDD = 3.3 V)
LVDS RECEIVER INPUTS (A[15:0]_x, B[15:0]_x, DCIA_x, DCIB_x)
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH to VIDTHL
Receiver Differential Input Impedance, RIN
LVDS Input Rate, fINTERFACE (See Table 4)
LVDS RECEIVER INPUTS (FRAMEA_x, FRAMEB_x)
Input Voltage Range, VIA or VIB
DAC CLOCK INPUT (CLK_P, CLK_N)
Differential Peak-to-Peak Voltage
Common-Mode Voltage (Self-Biasing, AC-Coupled)
Maximum Clock Rate
REFERENCE CLOCK INPUT (REFCLK_x/SYNC_x)
Differential Peak-to-Peak Voltage
Common-Mode Voltage (Self-Biasing, AC-Coupled)
Maximum Clock Rate
Minimum Clock Rate (PLL Enabled)
Loop Divider = /2
Loop Divider = /4
Loop Divider = /8
Loop Divider = /16
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High (tPWH)
Minimum Pulse Width Low (tPWL)
Set-Up Time, SDI to SCLK (tDS)
Hold Time, SDI to SCLK (tDH)
Data Valid, SDO to SCLK (tDV)
Setup time, CS to SCLK (tDCSB)
Min
Typ
1.2
2.0
1.4
2.4
825
−100
20
80
825
100
500
1.25
1000
100
500
1.25
500
40
1.9
0.2
23
1.4
Max
0.6
0.8
0.4
0.4
1575
+100
120
1200
1575
2000
2000
125
62.5
31.25
15.625
12.5
12.5
Unit
V
V
V
V
V
V
V
V
mV
mV
mV
MSPS
mV
mV
V
MSPS
mV
V
MSPS
MSPS
MSPS
MSPS
MSPS
MHz
ns
ns
ns
ns
ns
ns
Rev. B | Page 6 of 72
 

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