DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

AD9125-M5375-EBZ View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
AD9125-M5375-EBZ Datasheet PDF : 56 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD9125
Pin No.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Mnemonic
NC
DVDD18
DVSS
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
DVDD18
DVSS
D3
D2
D1
D0
DVDD18
SDO
SDIO
SCLK
CS
RESET
NC
AVSS
AVDD33
IOUT2P
IOUT2N
AVDD33
AVSS
REFIO
FSADJ
AVSS
AVDD33
IOUT1N
IOUT1P
AVDD33
REFCLKN
REFCLKP
CVDD18
CVDD18
EPAD
Description
No Connect.
1.8 V Digital Supply.
Digital Common.
Data Bit 15.
Data Bit 14.
Data Bit 13.
Data Bit 12.
Data Bit 11.
Data Bit 10.
Data Bit 9.
Data Bit 8.
Data Bit 7.
Data Bit 6.
Data Bit 5.
Data Bit 4.
1.8 V Digital Supply.
Digital Supply Common.
Data Bit 3.
Data Bit 2.
Data Bit 1.
Data Bit 0.
1.8 V Digital Supply.
Serial Port Data Output (CMOS levels with respect to IOVDD).
Serial Port Data Input/Output (CMOS levels with respect to IOVDD).
Serial Port Clock Input (CMOS levels with respect to IOVDD).
Serial Port Chip Select. Active Low (CMOS levels with respect to IOVDD).
Reset. Active Low (CMOS levels with respect to IOVDD).
No Connect.
Analog Supply Common.
3.3 V Analog Supply.
Q DAC Positive Current Output.
Q DAC Negative Current Output.
3.3 V Analog Supply.
Analog Supply Common.
Voltage Reference. Nominally 1.2 V output. Should be decoupled to analog common.
Full-Scale Current Output Adjust. Place a 10 kΩ resistor on the analog common.
Analog Common.
3.3 V Analog Supply.
I DAC Negative Current Output.
I DAC Positive Current Output.
3.3 V Analog Supply.
PLL Reference Clock Input, Negative. This pin has a secondary function as the SYNC input.
PLL Reference Clock Input, Positive. This pin has a secondary function as the SYNC input.
1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry.
1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry.
Exposed pad must be connected to AVSS. This provides an electrical, thermal, and mechanical connection
to the PCB.
Rev. 0 | Page 9 of 56
 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]