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AD9122-M5372-EBZ View Datasheet(PDF) - Analog Devices

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Description
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AD9122-M5372-EBZ Datasheet PDF : 56 Pages
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AD9122
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 1.8 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input VIN Logic High (IOVDD = 1.8 V)
Input VIN Logic High (IOVDD = 2.5 V)
Input VIN Logic Low (IOVDD = 1.8 V)
Input VIN Logic Low (IOVDD = 2.5 V)
CMOS OUTPUT LOGIC LEVEL
Output VOUT Logic High
Output VOUT Logic High
Output VOUT Logic Low
Output VOUT Logic Low
LVDS RECEIVER INPUTS1
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH to VIDTHL
Receiver Differential Input Impedance, RIN
LVDS Input Rate
DAC CLOCK INPUT (DACCLKP, DACCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
REFCLK INPUT (REFCLKP, REFCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
REFCLK Frequency (PLL Mode)
REFCLK Frequency (SYNC Mode)
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High (tPWH)
Minimum Pulse Width Low (tPWOL)
Setup Time, SDI to SCLK (tDS)
Hold Time, SDI to SCLK (tDH)
Data Valid, SDO to SCLK (tDV)
Setup Time, CS to SCLK (tDCSB)
Conditions
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 1.8 V
IOVDD = 2.5 V
See Table 5
Self biased input, ac couple
1 GHz ≤ fVCO ≤ 26 Hz
See Multichip Synchronization section for conditions
Min Typ Max Unit
1.2
V
1.6
V
0.6 V
0.8 V
1.4
V
1.8
V
0.4 V
0.4 V
825
1575 mV
−100
+100 mV
20
mV
80
120 Ω
100
1200
500 2000 mV
1.25
V
MSPS
100
500 2000 mV
1.25
V
15.625
600 MHz
0
600 MHz
40
MHz
12.5 ns
12.5 ns
1.9
ns
0.2
ns
23
ns
1.4
ns
1 LVDS receiver is compliant to the IEEE 1596 reduced range link, unless otherwise noted.
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3.
Parameter
LATENCY (DACCLK Cycles)
1× Interpolation (With or Without Modulation)
2× Interpolation (With or Without Modulation)
4× Interpolation (With or Without Modulation)
8× Interpolation (With or Without Modulation)
Inverse Sinc
Fine Modulation
Power-Up Time
Min
Typ
Max
Unit
64
Cycles
135
Cycles
292
Cycles
608
Cycles
20
Cycles
8
Cycles
260
ms
Rev. 0 | Page 5 of 56
 

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