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AD9129BBCZRL View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
AD9129BBCZRL Datasheet PDF : 68 Pages
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AD9119/AD9129
Data Sheet
LVDS DIGITAL SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. LVDS drivers and receivers are compatible with the IEEE
Standard 1596.3-1996, unless otherwise noted.
Table 2.
Parameter
LVDS DATA INPUTS (P1_D[13:0]P, P1_D[13:0]N,
P0_D[13:0]P, P0_D[13:0]N)
Input Voltage Range
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input Impedance
LVDS Input Rate
Input Capacitance
LVDS CLOCK INPUTS (DCI_P, DCI_N)
Input Voltage Range
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input Impedance
Maximum Clock Rate
LVDS CLOCK OUTPUTS (DCO_P, DCO_N)
Output Voltage High
Output Voltage Low
Output Differential Voltage
Output Offset Voltage
Output Impedance, Single-Ended
RO Mismatch Between A and B
Change in |VOD| Between Setting 0 and Setting 1
Change in VOS Between Setting 0 and Setting 1
Output Current
Driver Shorted to Ground
Drivers Shorted Together
Power-Off Output Leakage
Maximum Clock Rate
Symbol
Test Conditions/Comments
Px_DxP = VIA, Px_DxN = VIB
VIA, VIB
VIDTH
VIDTHH − VIDTHL
RIN
Min
825
−100
80
1400
VIA, VIB
VIDTH
VIDTHH − VIDTHL
RIN
VOA, VOB
VOA, VOB
|VOA|, |VOB|
VOS
RO
∆RO
|∆VOD|
∆VOS
DCI_P = VIA, DCI_N = VIB
DCO_P = VOA, DCO_N = VOB,
100 Ω termination
Register 0x7C[7:6] = 01b (default)
825
−225
80
700
1025
200
1150
80
ISA, ISB
ISAB
|IXA|, |IXB|
700
Typ Max Unit
1575 mV
+100 mV
20
mV
120 Ω
MSPS
1.2
pF
1575 mV
+225 mV
20
mV
120 Ω
MHz
1375 mV
mV
225 250 mV
1250 mV
100 120 Ω
10 %
25 mV
25 mV
20 mA
4
mA
10 µA
MHz
HSTL DIGITAL SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. HSTL receiver levels are compatible with the EIA/JEDEC
JESD8-6 standard, unless otherwise noted.
Table 3.
Parameter
HSTL DATA INPUTS (P1_D[13:0]P, P1_D[13:0]N,
P0_D[13:0]P, P0_D[13:0]N)
Common-Mode Input Voltage Range
Differential Input Voltage
Receiver Differential Input Impedance
HSTL Input Rate
Input Capacitance
HSTL CLOCK INPUT (DCI_P, DCI_N)
Common-Mode Input Voltage Range
Differential Input Voltage
Receiver Differential Input Impedance
Maximum Clock Rate
Symbol
VIA, VIB
RIN
VIA, VIB
RIN
Test Comments/Conditions Min
Px_DxP = VIA, Px_DxN = VIB
0.68
200
80
DCI_P = VIA, DCI_N = VIB
0.68
450
80
700
Rev. 0 | Page 4 of 68
Typ Max Unit
0.9
120
1400
1.2
V
mV
Ω
MSPS
pF
0.9 mV
mV
120 Ω
MHz
 

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