AD9106
Data Sheet
DIGITAL TIMING SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2; IOUTFS = 4 mA, maximum sample rate,
unless otherwise noted.
Table 3.
Parameter
DAC CLOCK INPUT (CLKIN)
Maximum Clock Rate
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time SDIO to SCLK
Hold Time SDIO to SCLK
Output Data Valid SCLK to SDO or SDIO
Setup Time CSE to SCLK
A
Min
Typ
Max
Unit
180
MSPS
80
MHz
6.25
ns
6.25
ns
4.0
ns
5.0
ns
6.2
ns
4.0
ns
DIGITAL TIMING SPECIFICATIONS (1.8 V)
TMIN to TMAX, AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO = 1.8 V, IOUTFS = 4 mA, maximum sample rate, unless
otherwise noted.
Table 4.
Parameter
DAC CLOCK INPUT (CLKIN)
Maximum Clock Rate
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time SDIO to SCLK
Hold Time SDIO to SCLK
Output Data Valid SCLK to SDO or SDIO
Setup Time CSE to SCLK
A
A
Min
Typ
Max
Unit
180
MSPS
80
MHz
6.25
ns
6.25
ns
4.0
ns
5.0
ns
8.8
ns
4.0
ns
Rev. A | Page 6 of 48