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AD9102BCPZRL7 View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
AD9102BCPZRL7 Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9102
SCLK 1
SDIO 2
DGND 3
DLDO2 4
DVDD 5
DLDO1 6
SDO/SDI2/DOUT 7
CS 8
AD9102
TOP VIEW
(Not to Scale)
24 CAL_SENSE
23 CLKVDD
22 CLDO
21 CLKP
20 CLKN
19 CLKGND
18 REFIO
17 NC
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY
CONNECTED TO A COPPER GROUND PLANE FOR ENHANCED
ELECTRICAL AND THERMAL PERFORMANCE.
Figure 2. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. Mnemonic
Description
1
SCLK
SPI Clock Input.
2
SDIO
SPI Data Input/Output. Primary bidirectional data line for the SPI port.
3
DGND
Digital Ground.
4
DLDO2
1.8 V Internal Digital LDO1 Outputs. When the internal digital LDO1 is enabled, bypass this pin with a 0.1 μF
capacitor.
5
DVDD
3.3 V External Digital Power Supply. DVDD defines the level of the digital interface of the AD9102 (SPI interface).
6
DLDO1
1.8 V Internal Digital LDO2 Outputs. When the internal digital LDO2 is enabled, bypass this pin with a 0.1 μF
capacitor.
7
SDO/SDI2/DOUT Digital I/O Pin.
In 4-wire SPI mode (SDO), this pin outputs the data from the SPI.
In double-SPI mode (SDI2), this pin is a second data input line for the SPI port that writes to the SRAM.
In data out mode (DOUT), this terminal is a programmable pulse output.
8
CS
SPI Port Chip Select, Active Low.
9
RESET
Active Low Reset Pin. Resets registers to their default values.
10
NC
Not Connected. Do not connect to this pin.
11
NC
Not Connected. Do not connect to this pin.
12
AVDD2
1.8 V to 3.3 V Power Supply Input.
13
NC
Not Connected. Do not connect to this pin.
14
NC
Not Connected. Do not connect to this pin.
15
AGND
Analog Ground.
16
NC
Not Connected. Do not connect to this pin.
17
NC
Not Connected. Do not connect to this pin.
18
REFIO
DAC Voltage Reference Input/Output.
19
CLKGND
Clock Ground.
20
CLKN
Clock Input, Negative Side.
21
CLKP
Clock Input, Positive Side.
22
CLDO
Clock Power Supply Output (Internal Regulator in Use), Clock Power Supply Input (Internal Regulator Bypassed).
23
CLKVDD
Clock Power Supply Input.
24
CAL_SENSE
Sense Input for Automatic IOUTFS Calibration.
25
FSADJ
26
AGND
External Full-Scale Current Output Adjust for DAC or Full-Scale Current Output Adjust Reference for
Automatic IOUTFS Calibration.
Analog Ground.
27
IOUTP
DAC Current Output, Positive Side.
28
IOUTN
DAC Current Output, Negative Side.
Rev. 0 | Page 9 of 36
 

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