AD9102 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9102 Datasheet PDF : 36 Pages
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AD9102
Data Sheet
FSADJ Register (DACRSET, Address 0x0C)
Table 21. Bit Descriptions for DACRSET
Bits Bit Name
Settings Description
15
DAC_RSET_EN
To write, enable the internal RSET resistor for the DAC. To read, enable RSET
for DAC 1 during calibration mode.
[14:13] RESERVED
[12:8] DAC_RSET_CAL
Digital control for the value of the RSET resistor for the DAC after
calibration; read only.
[7:5] RESERVED
[4:0] DAC_RSET
Digital control to set the value of the RSET resistor in the DAC .
Calibration Register (CALCONFIG, Address 0x0D)
Table 22. Bit Descriptions for CALCONFIG
Bits Bit Name
Settings Description
15
RESERVED
14
COMP_OFFSET_OF
Compensation offset calibration value overflow.
13
COMP_OFFSET_UF
Compensation offset calibration value underflow.
12
RSET_CAL_OF
RSET calibration value overflow.
11
RSET_CAL_UF
RSET calibration value underflow.
10
GAIN_CAL_OF
Gain calibration value overflow.
9
GAIN_CAL_UF
Gain calibration value underflow.
8
CAL_RESET
Pulse this bit high and low to reset the calibration results.
7
CAL_MODE
Read-only flag indicating calibration is being used.
6
CAL_MODE_EN
Enables the gain calibration circuitry.
[5:4] COMP_CAL_RNG
Offset calibration range.
3
CAL_CLK_EN
Enables the calibration clock to the calibration circuitry.
[2:0] CAL_CLK_DIV
Sets divider from the DAC clock to the calibration clock.
Reset
0x0
0x0
0x00
0x0
0x0A
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
R
RW
RW
Access
RW
R
R
R
R
R
R
RW
R
RW
RW
RW
RW
Comp Offset Register (COMPOFFSET, Address 0x0E)
Table 23. Bit Descriptions for COMPOFFSET
Bits Bit Name
Settings Description
15 RESERVED
[14:8] COMP_OFFSET_CA
L
The result of the offset calibration for the comparator.
[7:2] RESERVED
1
CAL_FIN
Read-only flag indicating calibration is completed.
0
START_CAL
Start a calibration cycle.
Update Pattern Register (RAMUPDATE, Address 0x1D)
Table 24. Bit Descriptions for RAMUPDATE
Bits Bit Name
Settings Description
[15:1] RESERVED
0
UPDATE
Update all SPI settings with a new configuration (self-clearing).
Reset
0x0
0x00
0x00
0x0
0x0
Access
RW
R
RW
R
RW
Reset
0x0000
0x0
Access
RW
RW
Rev. 0 | Page 30 of 36
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