Data Sheet
AD9102
Clock Control Register (CLOCKCONFIG, Address 0x02)
Table 17. Bit Descriptions for CLOCKCONFIG
Bits Bit Name
Settings Description
[15:12] RESERVED
11
DIS_CLK
Disable the analog clock to the DAC output of the clock distribution block.
10
RESERVED
9
RESERVED
Disable the analog clock to the DAC3 output of the clock distribution block.
8
RESERVED
Disable the analog clock to the DAC4 output of the clock distribution block.
7
DIS_DCLK
Disable the clock to core digital block.
6
CLK_SLEEP
Enables a very low power clock mode.
5
CLK_PDN
Disables and powers down the main clock receiver. No clocks are active in
the part.
4
EPS
Enable Power Save. This enables a low power option for clock receiver but
maintains low jitter performance on the DAC clock rising edge. The DAC
clock falling edge is substantially degraded.
3
DAC_INV_CLK
Cannot use EPS while using this bit. Inverts the clock inside DAC Core 1
allowing a 180° phase shift in DAC update timing.
[2:0] RESERVED
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reference Resistor Register (REFADJ, Address 0x03)
Table 18. Bit Descriptions for REFADJ
Bits Bit Name
Settings
[15:6] RESERVED
[5:0] BGDR
Description
Adjusts the on-chip REFIO voltage level (see Figure 35).
Reset
0x000
0x00
Access
RW
RW
DAC Analog Gain Register (DACAGAIN, Address 0x07)
Table19. Bit Descriptions for DACAGAIN
Bits Bit Name
Settings Description
15
RESERVED
[14:8] DAC_GAIN_CAL
DAC analog gain calibration output; read only
7
RESERVED
[6:0] DAC_GAIN
DAC analog gain control while not in calibration mode, twos complement
Reset
0x0
0x00
0x0
0x00
Access
RW
R
RW
RW
DAC Analog Gain Range Register (DACRANGE, Address 0x08)
Table20. Bit Descriptions for DACRANGE
Bits Bit Name
Settings Description
[15:2] RESERVED
[1:0] DAC_GAIN_RNG
DAC gain range control.
Reset
0x00
0x0
Access
RW
RW
Rev. 0 | Page 29 of 36