AD9102 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9102 Datasheet PDF : 36 Pages
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AD9102
Data Sheet
REGISTER DESCRIPTIONS
SPI Control Register (SPICONFIG, Address 0x00)
Table 15. Bit Descriptions for SPICONFIG
Bits Bit Name
Settings Description
15
LSBFIRST
LSB first selection.
0
MSB first per SPI standard (default).
1
LSB first per SPI standard.
14
SPI3WIRE
Selects if SPI is using 3-wire or 4-wire interface.
0
4-wire SPI.
1
3-wire SPI.
13
RESET
Executes software reset of SPI and controllers, reloads default register values,
except Register 0x00.
0
Normal status.
1
Reset whole register map, except 0x0000.
12
DOUBLESPI
Double SPI data line.
0
The SPI port has only 1 data line and can be used as a 3-wire or 4-wire interface.
1
The SPI port has two data lines both bi-directional defining a pseudo dual 3-
wire interface where CS and SCLK are shared between the two ports. This mode
is available only for RAM data read or write.
11
SPI_DRV
Double drive ability for SPI output.
0
Single SPI output drive ability.
1
Two time drive ability on SPI output.
10
DOUT_EN
Enable DOUT signal on SDO/SDI2/DOUT pin.
0
SDO/SDI2 function input/output.
1
DOUT function output.
[9:6] RESERVED
5
DOUT_ENM1
Enable DOUT signal on SDO/SDI2/DOUT pin.
4
SPI_DRVM1
Double drive ability for SPI output.
DOUBLESPIM1
Doube SPI data line.
2
RESETM1
Executes software reset of SPI and controllers, reloads default register values,
except Register 0x00.
1
SPI3WIREM1
Selects whether SPI uses a 3-wire or 4-wire interface.
0
LSBFIRSTM1
LSB first selection.
Reset Access
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
RW
RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
1 SPICONFIG[10:15] must always be set to the mirror of SPICONFIG[5:0] to allow easy recovery of the SPI operation when LSBFIRST bit is set incorrectly. (Bit 15 = Bit 0, Bit 14 = Bit 1,
Bit 13 = Bit 2, Bit 12 = Bit 3, Bit 11 = Bit 4, and Bit 10 = Bit 5.)
Power Status Register (POWERCONFIG, Address 0x01)
Table 16. Bit Descriptions for POWERCONFIG
Bits Bit Name
Settings Description
[15:12] RESERVED
11
CLK_LDO_STAT
Read-only flag indicating CLKVDD LDO is on.
10
DIG1_LDO_STAT
Read-only flag indicating DVDD1 LDO is on.
9
DIG2_LDO_STAT
Read-only flag indicating DVDD2 LDO is on.
8
PDN_LDO_CLK
Disable the CLKVDD LDO. An external supply is required.
7
PDN_LDO_DIG1
Disable the DVDD1 LDO. An external supply is required.
6
PDN_LDO_DIG2
Disable the DVDD2 LDO. An external supply is required.
5
REF_PDN
Power down on-chip REFIO.
4
REF_EXT
Always set to 0.
3
DAC_SLEEP
Disable DAC output current.
2
RESERVED
Disable DAC2 output current.
1
RESERVED
Disable DAC3 output current.
0
RESERVED
Disable DAC4 output current.
Rev. 0 | Page 28 of 36
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
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