AD9102
Data Sheet
When using automatic calibration, the following board level
connections are required:
1. Connect the FSADJ pin and the CAL_SENSE pin
together.
2. Install a resistor between the CAL_SENSE pin and
AGND. To calculate the value of this resistor, use the
following equation:
RCAL_SENSE = 32 × VREFIO/IOUTFS
where IOUTFS is the target full-scale current.
Automatic calibration uses an internal clock. This calibration
clock is equal to the DAC clock divided by the division factor
chosen by the CAL_CLK_DIV bits of Register 0x0D. Each
calibration cycle is between 4 and 512 DAC clock cycles,
depending on the value of CAL_CLK_DIV[2:0]. The frequency
of the calibration clock should be less than 500 kHz.
To perform an automatic calibration, the following steps must
be followed:
1. Set the calibration ranges in Register 0x008[7:0] and
Register 0x0D[5:4] to their minimum values to allow best
calibration.
2. Enable the calibration clock bit, CAL_CLK_EN, in Register
0x0D.
3. Set the divider ratio for the calibration clock by setting the
CAL_CLK_DIV[2:0] bits in Register 0x0D. The default is 512.
4. Set the CAL_MODE_EN bit in Register 0x0D to Logic 1.
5. Set the START_CAL bit in Register 0x0E to Logic 1. This
begins the calibration of the comparator, RSET, and gain.
6. The CAL_MODE flag in Register 0x0D goes to Logic 1 while
the part is calibrating. The CAL_FIN flag in Register 0x0E
goes to Logic 1 when the calibration is complete.
7. Set the START_CAL bit in Register 0x0E to Logic 0.
8. After calibration, verify that the overflow and underflow
flags in Register 0x0D are not set (Bits[14:8]). If they are
set, change the corresponding calibration range to the next
larger range and start from Step 5 again.
9. If no flag is set, read the DAC_RSET_CAL and
DAC_GAIN_CAL values in the DACRSET and
DACAGAIN registers respectively and write them into
their corresponding DAC_RSET and DAC_GAIN register
fields.
10. Reset the CAL_MODE_EN bit and the calibration clock
bit, CAL_CLK_EN, in Register 0x0D to Logic 0 to disable
the calibration clock.
11. Set the CAL_MODE_EN bit in Register 0x0D to Logic 0.
This points the RSET and gain control muxes toward the
regular registers.
12. Disable the calibration clock bit CAL_CLK_EN in
Register 0x0D.
To reset the calibration, pulse the CAL_RESET bit in Register 0x0D
to Logic 1 and Logic 0, pulse the RESET pin, or pulse the
RESET bit in the SPICONFIG register.
CLOCK INPUT
For optimum DAC performance, the AD9102 clock input signal
pair (CLKP/CLKN) should be a very low jitter, fast rise time
differential signal. The clock receiver generates its own common-
mode voltage, requiring these two inputs to be ac-coupled.
Figure 36 shows the recommended interface to a number of
Analog Devices LVDS clock drivers that work well with the
AD9102. A 100 Ω termination resistor and two 0.1 μF coupling
capacitors are used. Figure 38 is an interface to an Analog Devices
differential PECL driver. Figure 39 shows a single-ended to
differential converter using a balun driving CLKP/CLKN.
CLK+
0.1µF
CLK
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
0.1µF
CLKP
CLK–
50Ω*
LVDS DRIVER
0.1µF
CLK
50Ω*
100Ω
0.1µF
AD9102
CLKN
*50Ω RESISTORS ARE OPTIONAL.
Figure 36. Differential LVDS Clock Input
In applications where the analog output signals are at low
frequencies, the AD9102 clock input can be driven with a
single-ended CMOS signal. Figure 37 shows such an interface.
CLKP is driven directly from a CMOS gate, and the CLKN pin is
bypassed to ground with a 0.1 μF capacitor in parallel with a
39 kΩ resistor. The optional resistor is a series termination.
CLK+
0.1µF
50Ω
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
CLK
CMOS DRIVER
CLK
OPTIONAL
100Ω
CLKP
AD9102
0.1µF
CLKN
39kΩ
CLK+
CLK–
50Ω*
Figure 37. Single-Ended 1.8 V CMOS Sample Clock
0.1µF
CLK
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
0.1µF
CLKP
PECL DRIVER
0.1µF
CLK
50Ω*
240Ω
100Ω
0.1µF
240Ω
AD9102
CLKN
*50Ω RESISTORS ARE OPTIONAL.
Figure 38. Differential PECL Sample Clock
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