AD7927BRU-REEL View Datasheet(PDF) - Analog Devices
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AD7927BRU-REEL Datasheet PDF : 29 Pages
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AD7927
Data Sheet
SERIAL INTERFACE
Figure 26 shows the detailed timing diagram for serial inter-
facing to the AD7927. The serial clock provides the conversion
clock and also controls the transfer of information to and from
the AD7927 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and
requires 16 SCLK cycles to complete. The track-and-hold goes
back into track on the 14th SCLK falling edge as shown in
Figure 26 at Point B, except when the write is to the shadow
register, in which case the track-and-hold does not return to
track until the rising edge of CS, that is, Point C in Figure 27.
On the 16th SCLK falling edge the DOUT line goes back into
three-state. If the rising edge of CS occurs before 16 SCLKs have
elapsed, the conversion is terminated and the DOUT line goes
back into three-state and the control register is not be updated;
otherwise DOUT returns to three-state on the 16th SCLK falling
edge, as shown in Figure 26. Sixteen serial clock cycles are
required to perform the conversion process and to access data
from the AD7927. For the AD7927, the 12 bits of data are
preceded by a leading zero and the three-channel address bits
(ADD2 to ADD0) identifying which channel the result
corresponds to. CS going low provides the leading zero to be
read in by the microcontroller or DSP. The three remaining
address bits and data bits are then clocked out by subsequent
SCLK falling edges beginning with the first address bit (ADD2)
thus the first falling clock edge on the serial clock has a leading
zero provided and also clocks out Address Bit ADD2. The final
bit in the data transfer is valid on the 16th falling edge, having
been clocked out on the previous (15th) falling edge.
Writing of information to the control register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the MSB
(that is, the WRITE bit) has been set to 1. If the control register
is programmed to use the shadow register, then the writing of
information to the shadow register takes place on all 16 SCLK
falling edges in the next serial transfer as shown for example on
the AD7927 in Figure 27. Two sequence options can be pro-
grammed in the shadow register. If the user does not want to
program a second sequence, then the eight LSBs should be filled
with zeros. The shadow register is updated upon the rising edge
of CS and the track-and-hold begins to track the first channel
selected in the sequence.
The 16-bit word read from the AD7927 always contains a leading
zero and three-channel address bits that the conversion result
corresponds to, followed by the 12-bit conversion result.
WRITING BETWEEN CONVERSIONS
As outlined in the Modes of Operation section, no less than 5 μs
should be left between consecutive valid conversions. However,
there is one case where this does not necessarily mean that at
least 5 μs should always be left between CS falling edges. Con-
sider the prior to a valid conversion. The user must write to the
part to tell it to power up before it can convert successfully. Once
the serial write to power up has finished, it may be desirable to
perform the conversion as soon as possible and not have to wait
a further 5 μs before bringing CS low for the conversion. In this
case, as long as there is a minimum of 5 μs between each valid
conversion, then only the quiet time between the CS rising edge
at the end of the write to power up and the next CS falling edge
for a valid conversion needs to be met (see Figure 28). Note that
when writing to the AD7927 between these valid conversions,
the DOUT line is not driven during the extra write operation,
as shown in Figure 28.
It is critical that an extra write operation as outlined previously
is never issued between valid conversions when the AD7927 is
executing through a sequence function, as the falling edge of CS
in the extra write would move the mux on to the next channel
in the sequence. This means when the next valid conversion
takes place, a channel result would have been missed.
CS
SCLK
t2
1
tCONVERT
t6
2
3
4
5
t3
t7
t4
DOUT
THREE-
ADD2
ADD1
ADD0
STATE
3 IDENTIFICATION BITS
ZERO t9
DB11
DB10
t10
DIN
WRITE SEQ
DONTC
ADD2
ADD1
ADD0
B
13
14
t5
DB2
DB1
tQUIET
15
16
t8
DB0
t11
THREE-STATE
DONTC
DONTC
DONTC
Figure 26. Serial Interface Timing Diagram
Rev. D | Page 22 of 28
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