AD7927(2003) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7927 Datasheet PDF : 20 Pages
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CS
SCLK
1
12
16
DOUT
1 LEADING ZERO + 3 CHANNEL IDENTIFIER BITS
+ CONVERSION RESULT
DIN
DATA IN TO CONTROL REGISTER/
SHADOW REGISTER
NOTES
1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES
2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES
Figure 12. Normal Mode Operation
Full Shutdown (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the AD7927 is powered down.
The part retains information in the Control Register during full
shutdown. The AD7927 remains in full shutdown until the power
management bits in the Control Register, PM1 and PM0, are
changed.
If a write to the Control Register occurs while the part is in full
shutdown, with the power management bits changed to PM0 =
PM1 = 1, Normal Mode, the part will begin to power up on the
CS rising edge. The track and hold that was in hold while the
part was in full shutdown will return to track on the 14th SCLK
falling edge. A full 16 SCLK transfer must occur to ensure the
Control Register contents are updated; however, the DOUT
line will not be driven during this wake-up transfer.
To ensure that the part is fully powered up, tPOWER UP should have
elapsed before the next CS falling edge; otherwise, invalid data
AD7927
will be read if a conversion is initiated before this time. Figure 13
shows the general diagram for this sequence.
Auto Shutdown (PM1 = 0, PM0 = 1)
In this mode, the AD7927 automatically enters shutdown at the
end of each conversion when the Control Register is updated. When
the part is in shutdown, the track and hold is in Hold Mode.
Figure 14 shows the general diagram of the operation of the
AD7927 in this mode. In Shutdown Mode all internal circuitry on
the AD7927 is powered down. The part retains information in
the Control Register during shutdown. The AD7927 remains in
shutdown until the next CS falling edge it receives. On this CS
falling edge, the track and hold that was in hold while the part
was in shutdown will return to track. Wake-up time from auto
shutdown is 1 ms maximum, and the user should ensure that
1 ms has elapsed before attempting a valid conversion. When
running the AD7927 with a 20 MHz clock, one dummy 16 SCLK
transfer should be sufficient to ensure the part is fully powered
up. During this dummy transfer the contents of the Control
Register should remain unchanged; therefore the WRITE bit
should be 0 on the DIN line.
Depending on the SCLK frequency used, this dummy transfer
may affect the achievable throughput rate of the part, with every
other data transfer being a valid conversion result. If, for example,
the maximum SCLK frequency of 20 MHz was used, the auto
shutdown mode could be used at the full throughput rate of
200 kSPS without affecting the throughput rate at all. Only a
portion of the cycle time is taken up by the conversion time and the
dummy transfer for wake-up.
PART IS IN FULL
SHUTDOWN
CS
1
SCLK
PART BEGINS TO POWER UP ON
CS RISING EDGE AS PM1 = PM0 = 1
t12
THE PART IS FULLY POWERED UP
ONCE tPOWER UP HAS ELAPSED
14
16
1
14
16
DOUT
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DIN
DATA IN TO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS. PM1 = 1, PM0 = 1
DATA IN TO CONTROL REGISTER/SHADOW REGISTER
TO KEEP THE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
Figure 13. Full Shutdown Mode Operation
CS
1
SCLK
PART ENTERS
SHUTDOWN ON CS
RISING EDGE AS
PM1 ؍0, PM0 ؍1
PART BEGINS
TO POWER
UP ON CS
FALLING EDGE
12
16
DUMMY CONVERSION
1
12
16
PART IS FULLY
POWERED UP
1
PART ENTERS
SHUTDOWN ON CS
RISING EDGE AS
PM1 ؍0, PM0 ؍1
12
16
DOUT
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DIN
REV. 0
DATA IN TO CONTROL/SHADOW REGISTER
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS, PM1 ؍0, PM0 ؍1
CONTROL REGISTER SHOULD NOT
CHANGE, WRITE BIT ؍0
DATA IN TO CONTROL/SHADOW REGISTER
TO KEEP PART IN THIS MODE, LOAD PM1 ؍0, PM0 ؍1
IN CONTROL REGISTER OR SET WRITE BIT = 0
Figure 14. Auto Shutdown Mode Operation
–15–
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