AD73411 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD73411 Datasheet PDF : 36 Pages
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AD73411
When BDMA booting is specified, the BDMA interface is set up
during reset to the following defaults: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
The ADSP-2100 Family Development Software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory-space-compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the ad-
dresses to boot memory must be constructed externally to the
AD73411. A0 is the only memory address bit provided by the
processor.
IDMA Port Booting
The AD73411 can also boot programs through its Internal DMA
port. If Mode C = 1, Mode B = 0 and Mode A = 1, the AD73411
boots from the IDMA port. IDMA feature can load as much on-
chip memory as desired. Program execution is held off until
on-chip program memory location 0 is written to.
Bus Request and Bus Grant (Full Memory Mode)
The AD73411 can relinquish control of the data and address buses
to an external device. When the external device requires access
to memory, it asserts the bus request (BR) signal. If the AD73411
is not performing an external memory access, it responds to
the active BR input in the following processor cycle by:
• Three-stating the data and address buses and the PMS,
DMS, BMS, CMS, IOMS, RD, WR output drivers
• Asserting the bus grant (BG) signal
• Halting program execution
If Go Mode is enabled, the AD73411 will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the AD73411 is performing an external memory access when
the external device asserts the BR signal, it will not three-state
the memory interfaces or assert the BG signal until the processor
cycle after the access completes. The instruction does not need
to be completed when the bus is granted. If a single instruction
requires two external memory accesses, the bus will be granted
between the two accesses.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the AD73411 is ready to execute
an instruction, but is stopped because the external bus is already
granted to another device. The other device can release the bus
by deasserting bus request. Once the bus is released, the AD73411
deasserts BG and BGH and executes the external memory access.
EZ-ICE® registered trademark of Analog Devices.
EZ-Tools™ registered trademark of Analog Devices.
Flag I/O Pins
The AD73411 has eight general-purpose programmable input/
output flag pins. They are controlled by two memory-mapped
registers. The PFTYPE register determines the direction, 1 =
output and 0 = input. The PFDATA register is used to read and
write the values on the pins. Data being read from a pin config-
ured as an input is synchronized to the AD73411’s clock. Bits
that are programmed as outputs will read the value being out-
put. The PF pins default to input during reset.
In addition to the programmable flags, the AD73411 has five
fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1, and
FL2. FL0–FL2 are dedicated output flags; FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.
Note: Pins PF0, PF1, PF2, and PF3 are also used for device
configuration during reset.
INSTRUCTION SET DESCRIPTION
The AD73411 assembly language instruction set has an algebraic
syntax that was designed for ease of coding and readability. The
assembly language, which takes full advantage of the processor’s
unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember cryp-
tic assembler mnemonics. For example, a typical arithmetic
add instruction, such as AR = AX0 + AY0, resembles a
simple equation.
• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
• The syntax is a superset ADSP-2100 Family assembly language
and is completely source-and object-code-compatible with other
family members. Programs may need to be relocated to utilize
on-chip memory and conform to the AD73411’s interrupt
vector and reset vector map.
• Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE®-COMPATIBLE SYSTEM
The AD73411 has on-chip emulation support and an ICE-Port,
a special set of pins that interface to the EZ-ICE. These features
allow in-circuit emulation without replacing the target system
processor by using only a 14-pin connection from the target
system to the EZ-ICE. Target systems must have a 14-pin con-
nector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
See the ADSP-2100 Family EZ-Tools™ data sheet for complete
information on ICE products.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
prior to issuing a chip reset command from the emulator user
interface. If you are using a passive method of maintaining
mode information (as discussed in Setting Memory Modes), it
does not matter that the mode information is latched by an
emulator reset. However, if using the RESET pin as a method
REV. 0
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