7314 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
7314 Datasheet PDF : 8 Pages
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AD7314–SPECIFICATIONS*
(TA = TMIN to TMAX, VDD = 2.65 V to 5.5 V, unless otherwise noted.)
Parameter
Min Typ Max Unit Test Conditions/Comments
TEMPERATURE SENSOR AND ADC
Accuracy
Resolution
Update Rate, tR
Temperature Conversion Time
± 2.0 ∞C
± 1.0
∞C
10
Bits
400
ms
25
ms
TA = –35∞C to +85∞C. VDD = 2.65 V to 2.9 V
TA = –35∞C to +85∞C. VDD = 3 V to 5.5 V
SUPPLIES
Supply Voltage
Supply Current
Normal Mode (Inactive)
Normal Mode (Active)
Shutdown Mode
Power Dissipation
Power Dissipation
1 SPS
10 SPS
100 SPS
2.65
5.5
V
250 300
mA
275
mA
1
mA
1.2
mA
1
mA
1
mA
860
mW
3
mW
3.3
mW
6
mW
For Specified Performance
Part Not Converting, VDD = 2.65 V to 2.9 V
Part Not Converting, VDD = 3 V to 5.5 V
Part Converting, VDD = 2.65 V to 2.9 V
Part Converting, VDD = 3 V to 5.5 V
VDD = 2.65 V to 2.9 V
VDD = 3 V to 5.5 V
VDD = 2.65 V. Using Normal Mode
(Auto Conversion)
VDD = 2.65 V. Using Shutdown Mode
DIGITAL INPUT
Input High Voltage, VIH
1.85
Input Low Voltage, VIL
Input High Voltage, VIH
2.4
Input Low Voltage, VIL
Input Current, IIN
Input Capacitance, CIN
DIGITAL OUTPUT
Output High Voltage, VOH
2.4
Output Low Voltage, VOL
Output Capacitance, COUT
*All specifications apply for –35∞C to +85∞C, unless otherwise noted.
Specifications subject to change without notice.
V
0.53 V
V
0.8
V
±1
mA
10
pF
V
0.4
V
50
pF
VDD = 2.65 V to 2.9 V
VDD = 2.65 V to 2.9 V
VDD = 3 V to 5.5 V
VDD = 3 V to 5.5 V
VIN = 0 V to VDD
All Digital Inputs
ISOURCE = ISINK = 200 mA
IOL = 200 mA
TIMING CHARACTERISTICS1, 2
(TA3 = TMIN to TMAX, VDD = 2.65 V to 5.5 V, unless otherwise noted. See Figure 1.)
Parameter
Limit
Unit
Comments
t1
0
ns min
CE to SCLK Setup Time
t2
50
ns min
SCLK High Pulse Width
t3
50
ns min
SCLK Low Pulse Width
t44
35
ns max
Data Access Time after SCLK Rising Edge
t5
20
ns min
Data Setup Time prior to SCLK Falling Edge
t6
0
ns min
Data Hold Time after SCLK Falling Edge
t7
0
ns min
CE to SCLK Hold Time
t84
40
ns max
CE to SDO High Impedance
NOTES
1Guaranteed by design and characterization, not production tested.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and are timed from a voltage level of 1.6 V.
3All specifications apply for –35∞C to +85∞C, unless otherwise noted.
4Measured with the load circuit of Figure 2.
Specifications subject to change without notice.
–2–
REV. A
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