AD5781
Data Sheet
Control Register
The control register controls the mode of operation of the AD5781.
Table 11. Control Register
MSB
DB23 DB22 DB21 DB20
R/W
Register address
R/W 0
1
0
DB19...DB11
Reserved
DB10
Reserved
DB9 DB8
LIN COMP
DB7 DB6 DB5
DB4
Control register data
SDODIS BIN/2sC
DB3
DACTRI
DB2
OPGND
DB1
RBUF
LSB
DB0
Reserved
Table 12. Control Register Functions
Function
Description
Reserved
These bits are reserved and should be programmed to zero.
RBUF
Output amplifier configuration control.
0: internal amplifier, A1, is powered up and resistors RFB and R1 are connected in series as shown in Figure 53. This allows
an external amplifier to be connected in a gain of two configurations. See the AD5781 Features section for further details.
1: (default) internal amplifier, A1, is powered down and resistors RFB and R1 are connected in parallel as shown in Figure 52
so that the resistance between the RFB and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the RFB and INV
pins to be used for input bias current compensation for an external unity gain amplifier. See the AD5781 Features section
for further details.
OPGND
Output ground clamp control.
0: DAC output clamp to ground is removed, and the DAC is placed in normal mode.
1: (default) DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode.
Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated.
Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit.
DACTRI
DAC tristate control.
0: DAC is in normal operating mode.
1: (default) DAC is in tristate mode.
BIN/2sC
DAC register coding select.
0: (default) DAC register uses twos complement coding.
1: DAC register uses offset binary coding.
SDODIS
SDO pin enable/disable control.
0: (default) SDO pin is enabled.
1: SDO pin is disabled (tristate).
LIN COMP
Linearity error compensation for varying reference input spans. See the AD5781 Features section for further details.
0 0 0 0 (Default) reference input span up to 10 V.
1 1 0 0 Reference input span of 20 V.
Clearcode Register
The clearcode register sets the value to which the DAC output is set when the CLR pin or CLR bit is asserted. The output value depends
on the DAC coding that is being used, either binary or twos complement. The default register value is 0.
Table 13. Clearcode Register
MSB
DB23
DB22
DB21
DB20
R/W
Register address
R/W
0
1
1
DB19
DB2
Clearcode register data
18-bits of data
LSB
DB1
DB0
X1
X1
1 X is don’t care.
Rev. E | Page 22 of 27