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AD5235 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD5235 Nonvolatile Memory, Dual 1024-Position Digital Potentiometer ADI
Analog Devices ADI
AD5235 Datasheet PDF : 32 Pages
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AD5235
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
measured using both VDD = 2.7 V and VDD = 5 V.
Table 2.
Parameter
Clock Cycle Time (tCYC)
CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay2
CLK to SDO Data Hold Time
CS High Pulse Width3
CS High to CS High3
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Store EEMEM Time4, 5
Read EEMEM Time4
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous)6
Preset Response Time to Wiper Setting6
Power-On EEMEM Restore Time6
FLASH/EE MEMORY RELIABILITY
Endurance7
Data Retention8
Symbol
t1
t2
t3
t4, t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t16
t17
tPRW
tPRESP
tEEMEM
Conditions
Clock level high or low
From positive CLK transition
From positive CLK transition
RP = 2.2 kΩ, CL < 20 pF
RP = 2.2 kΩ, CL < 20 pF
Applies to Instructions 0x2, 0x3
Applies to Instructions 0x8, 0x9, 0x10
PR pulsed low to refresh wiper positions
TA = 25°C
Min Typ1 Max Unit
20
ns
10
ns
1
tCYC
10
ns
5
ns
5
ns
40
ns
50
ns
50
ns
0
ns
10
ns
4
tCYC
0
ns
0.15 0.3
ms
15 50
ms
7
30
μs
10
ns
50
ns
30
μs
30
μs
1
100
100
MCycles
kCycles
Years
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Propagation delay depends on the value of VDD, RPULL-UP, and CL.
3 Valid for commands that do not activate the RDY pin.
4 The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 μs; CMD_9, CMD_10 ~ 7 μs;
CMD_2, CMD_3 ~ 15 ms; PR hardware pulse ~ 30 μs.
5 Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles.
6 Not shown in Figure 2 and Figure 3.
7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C.
8 Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Rev. E | Page 6 of 32
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