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AD5235 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD5235 Nonvolatile Memory, Dual 1024-Position Digital Potentiometer ADI
Analog Devices ADI
AD5235 Datasheet PDF : 32 Pages
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RESISTANCE TOLERANCE, DRIFT, AND
TEMPERATURE COEFFICIENT MISMATCH
CONSIDERATIONS
In rheostat mode operation, such as gain control, the tolerance
mismatch between the digital potentiometer and the discrete
resistor can cause repeatability issues among various systems
(see Figure 62). Because of the inherent matching of the silicon
process, it is practical to apply the dual-channel device in this
type of application. As such, R1 can be replaced by one of the
channels of the digital potentiometer and programmed to a
specific value. R2 can be used for the adjustable gain. Although it
adds cost, this approach minimizes the tolerance and temperature
coefficient mismatch between R1 and R2. This approach also
tracks the resistance drift over time. As a result, these less than
ideal parameters become less sensitive to system variations.
B R2 A
W
C1
R1*
AD8601
VO
Vi
+
U1
* REPLACED WITH ANOTHER
CHANNEL OF RDAC
Figure 62. Linear Gain Control with Tracking Resistance Tolerance,
Drift, and Temperature Coefficient
Note that the circuit in Figure 63 can track tolerance, temperature
coefficient, and drift in this particular application. The characteristic
of the transfer function is, however, a pseudo log rather than a
linear gain function.
R
AB
W C1
AD8601
VO
Vi
+
U1
Figure 63. Nonlinear Gain Control with Tracking Resistance Tolerance and Drift
AD5235
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the −3 dB bandwidth of the AD5235
(25 kΩ resistor) measures 125 kHz at half scale. Figure 17 provides
the large signal bode plot characteristics of the two available
resistor versions, 25 kΩ and 250 kΩ. A parasitic simulation model
is shown in Figure 64.
RDAC
25k
A
B
CA
11pF
CB
11pF
80pF
W
Figure 64. RDAC Circuit Simulation Model (RDAC = 25 kΩ)
The following code provides a macro model net list for the
25 kΩ RDAC:
.PARAM D = 1024, RDAC = 25E3
*
.SUBCKT DPOT (A, W, B)
*
CA A 0 11E-12
RWA A W {(1-D/1024)* RDAC + 30}
CW W 0 80E-12
RWB W B {D/1024 * RDAC + 30}
CB B 0 11E-12
*
.ENDS DPOT
Rev. E | Page 29 of 32
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